Texas Instruments SN74ALS652A-1DW, SN74ALS652A-1DWR, SN74ALS652A-1NT, SN74ALS652ADW, SN74ALS652ADWR Datasheet

SN54ALS652, SN54ALS653, SN54AS651, SN54AS652 SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

SDAS066F ± DECEMBER 1983 ± REVISED OCTOBER 1996

DBus Transceivers/Registers

DIndependent Registers and Enables for A and B Buses

DMultiplexed Real-Time and Stored Data

DChoice of True or Inverting Data Paths

DChoice of 3-State or Open-Collector Outputs to A Bus

DPackage Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs

	DEVICE	A OUTPUT	B OUTPUT	LOGIC
	SN74ALS651A,	3 State	3 State	Inverting
	'AS651
	SN54ALS652,
	SN74ALS652A,	3 State	3 State	True
	'AS652
	'ALS653	Open Collector	3 State	Inverting
	SN74ALS654	Open Collector	3 State	True

SN54ALS', SN54AS' . . . JT PACKAGE SN74ALS', SN74AS' . . . DW OR NT PACKAGE

	(TOP VIEW)
CLKAB					VCC
		1	24
SAB		2	23			CLKBA
OEAB		3	22			SBA
A1		4	21			OEBA
A2		5	20			B1
A3		6	19			B2
A4		7	18			B3
A5		8	17			B4
A6		9	16			B5
A7		10	15			B6
A8		11	14			B7
GND		12	13			B8

SN54ALS', SN54AS' . . . FK PACKAGE

(TOP VIEW)

OEAB SAB CLKAB NC V	CLKBA SAB
CC

description
					4		3		2		1		28			27 26
These devices consist of bus-transceiver circuits,			A1		5											25							OEBA
			A2		6											24							B1
D-type flip-flops, and control circuitry arranged for
			A3		7											23							B2
multiplexed transmission of data directly from the
			NC		8											22							NC
data bus or from the internal storage registers.
			A4		9											21							B3
Output-enable (OEAB and OEBA) inputs are
			A5		10											20							B4
provided to control the transceiver functions.
			A6		11											19							B5
Select-control (SAB and SBA) inputs are provided
					12 13 14						15 16 17 18
to select real-time or stored data transfer. The
circuitry used for select control eliminates the						A7		A8		GND		NC		B8		B7 B6
typical decoding glitch that occurs in a multiplexer

during the transition between stored and real-time

NC ± No internal connection

data. A low input level selects real-time data, and a high input level selects stored data. Figure 1

illustrates the four fundamental bus-management functions that can be performed with the octal bus transceivers and registers.

Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) terminals, regardless of the selector output-control terminals. When SAB and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. When all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last state.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1996, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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SN54ALS652, SN54ALS653, SN54AS651, SN54AS652

SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

SDAS066F ± DECEMBER 1983 ± REVISED OCTOBER 1996

description (continued)

The -1 versions of the SN74ALS651A and SN74ALS652A are identical to the standard versions except that the recommended maximum IOL for the -1 versions is increased to 48 mA. There are no -1 versions of the SN54ALS652, SN54ALS653, SN74ALS653, and SN74ALS654.

The SN54ALS' and SN54AS' families are characterized for operation over the full military temperature range of ±55°C to 125°C. The SN74ALS' and SN74AS' families are characterized for operation from 0°C to 70°C.

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN54ALS652, SN54ALS653, SN54AS651, SN54AS652 SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

SDAS066F ± DECEMBER 1983 ± REVISED OCTOBER 1996

BUS A

BUS B

BUS A

BUS B

3

21

1

23

2

22

3

21

1

23

2

22

OEAB

OEBA

CLKAB

CLKBA

SAB

SBA

OEAB

OEBA

CLKAB

CLKBA

SAB

SBA

L

L

X

X

X

L

H

H

X

X

L

X

REAL-TIME TRANSFER

REAL-TIME TRANSFER

BUS B TO BUS A

BUS A TO BUS B

BUS A

BUS B

BUS A

BUS B

3

21

1

23

2

22

3

21

1

23

2

22

OEAB

CLKAB

CLKBA

SAB

SBA

OEAB

CLKAB

CLKBA

SAB

SBA

OEBA

OEBA

X

H

↑

X

X

X

H

L

H or L

H or L

H

H

L

X

X

↑

X

X

L

H

↑

↑

X

X

STORAGE FROM

TRANSFER STORED DATA

A, B, OR A AND B

TO A AND/OR B

Pin numbers are for the DW, JT, and NT packages.

Figure 1. Bus-Management Functions

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

3

SN54ALS652, SN54ALS653, SN54AS651, SN54AS652

SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

SDAS066F ± DECEMBER 1983 ± REVISED OCTOBER 1996

FUNCTION TABLES

SN54ALS653, SN54AS651,

SN74ALS651A, SN74ALS653, SN74AS651

INPUTS

DATA I/O²

OPERATION OR FUNCTION

OEAB

OEBA

CLKAB

CLKBA

SAB

SBA

A1± A8

B1± B8

L

H

H or L

H or L

X

X

Input

Input

Isolation

L

H

↑

↑

X

X

Input

Input

Store A and B data

X

H

↑

H or L

X

X

Input

Unspecified³

Store A, hold B

H

H

↑

↑

X³

X

Input

Output

Store A in both registers

L

X

H or L

↑

X

X

Unspecified³

Input

Hold A, store B

L

L

↑

↑

X

X³

Output

Input

Store B in both registers

L

L

X

X

X

L

Output

Input

Real-time

B

data to A bus

L

L

X

H or L

X

H

Output

Input

Stored

B

data to A bus

H

H

X

X

L

X

Input

Output

Real-time

A

data to B bus

H

H

H or L

X

H

X

Input

Output

Stored

A

data to B bus

Stored

data to B bus and

H

L

H or L

H or L

H

H

Output

Output

A

stored B data to A bus

²The data output functions may be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data input functions are always enabled; i.e., data at the bus terminals is stored on every low-to-high transition on the clock inputs.

³Select control = L; clocks can occur simultaneously.

Select control = H; clocks must be staggered to load both registers.

SN54ALS652, SN54AS652,

SN74ALS652A, SN74ALS654, SN74AS652

			INPUTS				DATA I/O²		OPERATION OR FUNCTION
	OEAB	OEBA	CLKAB	CLKBA	SAB	SBA	A1± A8	B1± B8
	L	H	H or L	H or L	X	X	Input	Input	Isolation
	L	H	↑	↑	X	X	Input	Input	Store A and B data
	X	H	↑	H or L	X	X	Input	Unspecified³	Store A, hold B
	H	H	↑	↑	X³	X	Input	Output	Store A in both registers
	L	X	H or L	↑	X	X	Unspecified³	Input	Hold A, store B
	L	L	↑	↑	X	X³	Output	Input	Store B in both registers
	L	L	X	X	X	L	Output	Input	Real-time B data to A bus
	L	L	X	H or L	X	H	Output	Input	Stored B data to A bus
	H	H	X	X	L	X	Input	Output	Real-time A data to B bus
	H	H	H or L	X	H	X	Input	Output	Stored A data to B bus
	H	L	H or L	H or L	H	H	Output	Output	Stored A data to B bus and
									stored B data to A bus

² The data output functions may be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data input functions are always enabled; i.e., data at the bus terminals is stored on every low-to-high transition on the clock inputs.

³Select control = L; clocks can occur simultaneously.

Select control = H; clocks must be staggered to load both registers.

4	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN54ALS652, SN54ALS653, SN54AS651, SN54AS652 SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

SDAS066F ± DECEMBER 1983 ± REVISED OCTOBER 1996

logic symbols²

SN54AS651,	SN54ALS652, SN54AS652,
SN74ALS651A, SN74AS651	SN74ALS652A, SN74AS652

OEBA	21	EN1 [BA]					OEBA	21	EN1 [BA]
	3							3
OEAB		EN2 [AB]					OEAB		EN2 [AB]
	23							23
CLKBA		C4					CLKBA		C4
	22							22
SBA		G5					SBA		G5
	1							1
CLKAB		C6					CLKAB		C6
	2							2
SAB		G7					SAB		G7
					20								20
A1	4	≥ 1		5	4D	B1	A1	4	≥ 1		5	4D	B1
		1		5	1				1		5	1
		6D	7	≥ 1					6D	7	≥ 1
		1	7		2				1	7		2
	5				19			5					19
A2						B2	A2
													B2
A3	6				18	B3	A3	6					18
													B3
A4	7				17	B4	A4	7					17
													B4
A5	8				16	B5	A5	8					16
													B5
A6	9				15	B6	A6	9					15
													B6
A7	10				14	B7	A7	10					14
													B7
A8	11				13	B8	A8	11					13
													B8
		SN54ALS653, SN74ALS653							SN74ALS654
OEBA	21	EN1 [BA]					OEBA	21	EN1 [BA]
	3							3
OEAB		EN2 [AB]					OEAB		EN2 [AB]
	23							23
CLKBA		C4					CLKBA		C4
	22							22
SBA		G5					SBA		G5
	1							1
CLKAB		C6					CLKAB		C6
	2							2
SAB		G7					SAB		G7
					20								20
A1	4	≥ 1		5	4D	B1	A1	4	≥ 1		5	4D	B1
		1		5	1				1		5	1
		6D	7	≥ 1					6D	7	≥ 1
		1	7		2				1	7		2
	5				19			5					19
A2						B2	A2
													B2
A3	6				18	B3	A3	6					18
													B3
A4	7				17	B4	A4	7					17
													B4
A5	8				16	B5	A5	8					16
													B5
A6	9				15	B6	A6	9					15
													B6
A7	10				14	B7	A7	10					14
													B7
A8	11				13	B8	A8	11					13
													B8

² These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DW, JT, and NT packages.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

5

SN54ALS652, SN54ALS653, SN54AS651, SN54AS652

SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

SDAS066F ± DECEMBER 1983 ± REVISED OCTOBER 1996

logic diagrams (positive logic)
OEBA	21	SN54ALS653, SN54AS651,
	3	SN74ALS651A, SN74ALS653, SN74AS651
OEAB
CLKBA	23
SBA	22
CLKAB	1
SAB	2
		One of Eight Channels
		1D
		C1
A1	4	20
			B1
		1D
		C1
		To Seven Other Channels
OEBA	21	SN54ALS652, SN54AS652,
	3	SN74ALS652A, SN74ALS654, SN74AS652
OEAB
CLKBA	23
SBA	22
CLKAB	1
SAB	2
		One of Eight Channels
		1D
		C1
A1	4	20
			B1
		1D
		C1

To Seven Other Channels

Pin numbers shown are for the DW, JT, and NT packages.

6	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN54ALS652, SN54ALS653, SN54AS651, SN54AS652 SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

SDAS066F ± DECEMBER 1983 ± REVISED OCTOBER 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)²

Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . 7	V
Input voltage, VI: Control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . 7	V
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . 5.5	V
Operating free-air temperature range, TA: SN54ALS652 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±55°C to 125°C
SN74ALS651A, SN74ALS652A . . . . . . . . . . . . . . .	. . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±65°C to 150°C

²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

			SN74ALS651A			UNIT
			MIN	NOM	MAX
VCC	Supply voltage		4.5	5	5.5	V
VIH	High-level input voltage		2			V
VIL	Low-level input voltage				0.8	V
IOH	High-level output current				± 15	mA
IOL	Low-level output current				24	mA
					48³
fclock	Clock frequency		0		40	MHz
tw	Pulse duration	CLKBA or CLKAB high	12.5			ns
		CLKBA or CLKAB low	12.5
tsu	Setup time before CLKAB↑ or CLKBA↑	A or B	10			ns
th	Hold time after CLKAB↑ or CLKBA↑	A or B	0			ns
TA	Operating free-air temperature		0		70	°C

³ Applies only to the SN74ALS651A-1 and only if VCC is maintained between 4.75 V and 5.25 V

recommended operating conditions

					SN54ALS652			SN74ALS652A			UNIT
					MIN	NOM	MAX	MIN	NOM	MAX
VCC	Supply voltage				4.5	5	5.5	4.5	5	5.5	V
VIH	High-level input voltage				2			2			V
VIL	Low-level input voltage						0.7			0.8	V
IOH	High-level output current						± 12			± 15	mA
IOL	Low-level output current						12			24	mA
										48³
fclock	Clock frequency				0		35	0		40	MHz
tw	Pulse duration			CLKBA or CLKAB high	14.5			12.5			ns
				CLKBA or CLKAB low	14.5			12.5
tsu	Setup time before CLKAB↑ or CLKBA↑			A or B	15			10			ns
th	Hold time after CLKAB↑ or CLKBA↑			A or B	5			0			ns
TA	Operating free-air temperature				± 55		125	0		70	°C
³ Applies only to the SN74ALS652A-1 and only if V		CC		is maintained between 4.75 V and 5.25 V

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