Texas Instruments SN74ALS667NT, SN74ALS667NT3, SN74ALS666DW, SN74ALS666DWR, SN74ALS666NT Datasheet

SN74ALS666, SN74ALS667 8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES WITH 3-STATE OUTPUTS

SDAS227A ± JUNE 1984 ± REVISED JANUARY 1995

•3-State I/O-Type Read-Back Inputs

•Bus-Structured Pinout

•Choice of True or Inverting Logic

±SN74ALS666 . . . True Outputs

±SN74ALS667 . . . Inverted Outputs

•Preset and Clear Inputs

•Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic (NT) 300-mil DIPs

description

These 8-bit D-type transparent latches are designed specifically for storing the contents of the input data bus, plus reading back the stored data onto the input data bus. In addition, they provide a 3-state buffer-type output and are easily utilized in bus-structured applications.

While the latch enable (LE) is high, the Q outputs of the SN74ALS666 follow the data (D) inputs. The Q outputs of the SN74ALS667 provide the inverse of the data applied to its D inputs. The Q or Q output of both devices is in the high-impedance state if either output-enable (OE1 or OE2) input is at a high logic level.

Read back is provided through the read-back

control (OERB) input. When OERB is taken low, the data present at the output of the data latches

passes back onto the input data bus. When OERB is taken high, the output of the data latches is

isolated from the D inputs. OERB does not affect the internal operation of the latches; however, caution should be exercised to avoid a bus conflict.

The SN74ALS666 and SN74ALS667 are characterized for operation from 0°C to 70°C.

SN74ALS666 . . . DW OR NT PACKAGE

			(TOP VIEW)
								VCC
OERB				1	24
	OE1			2	23			OE2
	1D			3	22			1Q
	2D			4	21			2Q
	3D			5	20			3Q
	4D			6	19			4Q
	5D			7	18			5Q
	6D			8	17			6Q
	7D			9	16			7Q
	8D			10	15			8Q
	CLR			11	14			PRE
GND				12	13			LE

SN74ALS667 . . . DW OR NT PACKAGE

			(TOP VIEW)
						VCC
OERB			1	24
	OE1		2	23		OE2
	1D
			3	22		1Q
	2D
			4	21		2Q
	3D
			5	20		3Q
	4D
			6	19		4Q
	5D
			7	18		5Q
	6D
			8	17		6Q
	7D
			9	16		7Q
	8D
			10	15		8Q
	CLR		11	14		PRE
GND			12	13		LE

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1995, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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SN74ALS666, SN74ALS667

8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES WITH 3-STATE OUTPUTS

SDAS227A ± JUNE 1984 ± REVISED JANUARY 1995

logic symbols²

									SN74ALS666
			2					&									2
		OE1								EN2						OE1
			23														23
		OE2														OE2
			1															1
								EN3
OERB														OERB
			14					S										14
	PRE														PRE
			11					R										11
	CLR														CLR
13								C1						13
		LE														LE
3														3
		1D						1D		2		22	1Q			1D
								3
4												21		4
		2D											2Q			2D
5												20		5
		3D											3Q			3D
6												19		6
		4D											4Q			4D
												18
7													5Q	7
		5D														5D
												17
8													6Q	8
		6D														6D
												16
9													7Q	9
		7D														7D
												15
10													8Q	10
		8D														8D

² These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

SN74ALS667

&

EN2

EN3

S

R

C1

1D	2	22
3		1Q

21

2Q

20

3Q

19

4Q

18

5Q

17

6Q

16

7Q

15

8Q

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

				SN74ALS666, SN74ALS667
			8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES
				WITH 3-STATE OUTPUTS
				SDAS227A ± JUNE 1984 ± REVISED JANUARY 1995
	logic diagrams (positive logic)
		2	SN74ALS666
	OE1
		23
	OE2
		1
	OERB
	PRE	14
	CLR	11
	LE	13
		3	S
	1D		1D	22
			C1	1Q
			R
			To Seven Other Channels
		2	SN74ALS667
	OE1
		23
	OE2
		1
	OERB
	PRE	14
	CLR	11
	LE	13
		3	S
	1D		1D	22
			C1	1Q
			R
			To Seven Other Channels

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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