Texas Instruments TCM29C16AN, TCM29C16ADWR, TCM29C13ADW, TCM29C17ADWR, TCM29C17AN Datasheet

TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,

TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A

COMBINED SINGLE-CHIP PCM CODEC AND FILTER

SCTS030E ± AUGUST 1989 ± REVISED OCTOBER 1996

	D Replace Use of TCM2910A and TCM2911A	FEATURES TABLE
	in Tandem With TCM2912B/C	FEATURE	29C13A	29C14A	29C16A	29C17A
	D Reliable Silicon-Gate CMOS Technology		129C13A	129C14A	129C16A	129C17A
		Number of Pins:
	D Low Power Consumption:
		24		X
	Operating Mode . . . 80 mW Typical	20	X		X	X
	Power-Down Mode . . . 5 mW Typical	16
	D Excellent Power-Supply Rejection Ratio	μ-Law/A-Law Coding:	X	X	X
	Over Frequency Range of 0 Hz to 50 kHz	μ-Law
		A-Law	X	X
	D No External Components Needed for	Gain Timing Rates:
	Sample, Hold, and Autozero Functions	Variable Mode	X	X	X	X
	D Precision Internal Voltage References	64 kHz to 2.048 MHz
		Fixed Mode
	D Improved Version of TCM29C13 Series
		1.536 MHz	X	X
	and TCM129C13 Series	1.544 MHz	X	X
		2.048 MHz	X	X	X	X
	description	Loopback Test Capability		X
		8th-Bit Signaling		X
	The TCM29C13A, TCM29C14A, TCM29C16A,
	TCM29C17A, TCM129C13A, TCM129C14A,

TCM129C16A, and TCM129C17A are single-chip PCM codecs (pulse-code-modulated encoders and decoders) and PCM line filters. These devices provide all the functions required to interface a full-duplex (4-wire) voice telephone circuit with a time-division-multiplexed (TDM) system. These devices are intended to replace the TCM2910A or TCM2911A in tandem with the TCM2912C. Primary applications include:

•Line interface for digital transmission and switching of T1 carrier, PABX, and central office telephone systems

•Subscriber line concentrators

•Digital-encryption systems

•Digital voice-band data storage systems

•Digital signal processing

TCM29C13A, TCM129C13A								TCM29C14A, TCM129C14A								TCM29C16, TCM29C16A,
	DW OR N PACKAGE									DW PACKAGE						TCM129C16, TCM129C17A
			(TOP VIEW)								(TOP VIEW)						DW OR N PACKAGE
									VBB					VCC					(TOP VIEW)
	VBB		1	20		VCC					1	24					VBB						VCC
PWRO +			2	19		GSX		PWRO +			2	23		GSX						1	16
PWRO ±			3	18		ANLG IN ±		PWRO ±			3	22		ANLG IN ±		PWRO +				2	15		GSX
								GSR						ANLG IN +		PWRO ±				3	14		ANLG IN ±
GSR			4	17		ANLG IN +					4	21
			5	16		ANLG GND			PDN		5	20		ANLG GND			PDN			4	13		ANLG GND
	PDN
																DCLKR				5	12
CLKSEL			6	15		SIGX/ASEL		CLKSEL			6	19		NC									TSX/DCLKX
								ANLG LOOP						SIGX/ASEL		PCM IN				6	11		PCM OUT
DCLKR			7	14							7	18
						TSX/DCLKX
								SIGR								FSR/TSRE				7	10		FSX/TSXE
PCM IN			8	13		PCM OUT					8	17		TSX/DCLKX
								DCLKR						PCM OUT		DGTL GND				8	9		CLKR/CLKX
FSR/TSRE			9	12		FSX/TSXE					9	16
DGTL GND			10	11		CLKR/CLKX		PCM IN			10	15		FSX/TSXE
								FSR/TSRE			11	14		CLKX
								DGTL GND			12	13		CLKR

NC ± No internal connection

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1996, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

1

TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,

TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A

COMBINED SINGLE-CHIP PCM CODEC AND FILTER

SCTS030E ± AUGUST 1989 ± REVISED OCTOBER 1996

description (continued)

These devices are designed to perform the transmit encoding (A/D conversion) and receive decoding (D/A conversion) as well as the transmit and receive filtering functions in a pulse-code-modulated system. They are intended to be used at the analog termination of a PCM line or trunk.

The TCM29C13A, TCM29C13A, TCM29C16A, TCM29C17A, TCM129C13A, TCM129C14A, TCM129C16A, and TCM129C17A provide the band-pass filtering of the analog signals prior to encoding and after decoding. These combination devices perform the encoding and decoding of voice and call progress tones as well as the signaling and supervision information. These devices contain patented circuitry to achieve low transmit channel idle noise and are not recommended for applications in which the composite signals on the transmit side are below ±55 dBm0.

The TCM29C13A, TCM29C14A, TCM29C16A, and TCM29C17A are characterized for operation from 0°C to 70°C. The TCM129C13A, TCM129C14A, TCM129C16A, and TCM129C17A are characterized for operation from ±40°C to 85°C.

functional block diagram

	Transmit Section
ANLG IN+	Filter
ANLG IN ±
GSX

		Autozero
	Sample				PCM OUT
			Successive	Output
	and Hold	Comparator			TSX/DCLKX
			Approximation	Register
	and DAC
					SIGX/ASEL

		Analog-
	Reference	to-Digital	FSX/TSXE
		Control
			CLKX
		Logic

	Receive Section			Control
		Filter		Section
	Gain			³
GSR		Σ
	Set
			Buffer
PWRO ±			Sample	Digital-
				to-Analog
			and Hold
				Control
			and DAC
				Logic
PWRO+			Reference

FSR/TSRE

CLKR²

VCC VBB DGTL ANLG

GND GND

² TCM29C14A and TCM129C14A only.

³ TCM29C13A, TCM29C16A, TCM29C17A, TCM129C13A, TCM129C16A, and TCM129C17A only

		CLKSEL
	Control	PDN
	Logic
		ANLG
		LOOP²
	Input	PCM IN
	Register	DCLKR
		SIGR²

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,

TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A

COMBINED SINGLE-CHIP PCM CODEC AND FILTER

					SCTS030E ± AUGUST 1989 ± REVISED OCTOBER 1996
			Terminal Functions
	TERMINAL
		NO.
NAME	TCM29C13A	TCM29C14A	TCM29C16A	I/O	DESCRIPTION
			TCM29C17A
	TCM129C13A	TCM129C14A	TCM129C16A
			TCM129C17A
ANLG GND	16	20	13		Analog ground return for all internal voice circuits. ANLG GND is
					internally connected to DGTL GND.
ANLG IN +	17	21		I	Noninverting analog input to uncommitted transmit operational
					amplifier. ANLG IN + is internally connected to ANLG GND on
					TCM29C16A, TCM129C16A, TCM29C17A, and TCM129C17A.
ANLG IN ±	18	22	14	I	Inverting analog input to uncommitted transmit operational amplifier.
ANLG LOOP		7		I	Provides loopback test capability. When ANLG LOOP is high,
					PWRO + is internally connected to ANLG IN.
CLKR	11	13	9	I	Receive master clock and data clock for the fixed-data-rate mode.
					Receive master clock only for variable-data-rate mode. CLKR and
					CLKX are internally connected together for the TCM29C13A,
					TCM29C16A, TCM29C17A, TCM129C13A, TCM129C16A, and
					TCM129C17A.
CLKSEL	6	6		I	Clock-frequency selection. CLKSEL must be connected to VBB,
					VCC, or GND to reflect the master clock frequency. When tied to VBB,
					CLK is 2.048 MHz. When tied to GND, CLK is 1.544 MHz.
					When tied to VCC, CLK is 1.536 MHz.
CLKX	11	14	9	I	Transmit master clock and data clock for the fixed-data-rate mode.
					Transmit master clock only for variable-date-rate mode. CLKR and
					CLKX are internally connected for the TCM29C13A, TCM29C16A,
					TCM29C17A, TCM129C13A, TCM129C16A, and TCM129c17A.
DCLKR	7	9	5	I	Selects fixedor variable-data-rate operation. When DCLKR is
					connected to VBB, the device operates in the fixed-data-rate mode.
					When DCLKR is not connected to VBB, the device operates in the
					variable-data-rate mode and DCLKR becomes the receiver data
					clock, which operates at frequencies from 64 kHz to 2.048 MHz.
DGTL GND	10	12	8		Digital ground for all internal logic circuits. DGTL GND is internally
					connected to ANLG GND.
FSR/TSRE	9	11	7	I	Frame-synchronization clock input/time-slot enable for receive
					channel. In the fixed-data-rate mode, FSR distinguishes between
					signaling and nonsignaling frames by a doubleor single-length
					pulse, respectively. In the variable-data-rate mode, this signal must
					remain high for the duration of the time slot. The receive channel
					enters the standby state when FSR is TTL low for 300 ms.
FSX/TSXE	12	15	10	I	Frame-synchronization clock input/time-slot enable for transmit
					channel. FSX/TSXE operates independently of, but in an analagous
					manner to, FSR/TSRE. The transmit channel enters the standby
					state when FSX is low for 300 ms.
GSR	4	4		I	Input to the gain-setting network on the output power amplifier.
					Transmission level can be adjusted over a 12-dB range depending
					upon the voltage at GSR.
GSX	19	23	15	O	Output terminal of internal uncommitted operational amplifier.
					Internally, this is the voice signal input to the transmit filter.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

3

TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,

TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A

COMBINED SINGLE-CHIP PCM CODEC AND FILTER

SCTS030E ± AUGUST 1989 ± REVISED OCTOBER 1996

Terminal Functions (Continued)

				TERMINAL
					NO.
	NAME			TCM29C13A	TCM29C14A	TCM29C16A	I/O	DESCRIPTION
						TCM29C17A
				TCM129C13A	TCM129C14A	TCM129C16A
						TCM129C17A
	PCM IN			8	10	6	I	Receive PCM input. PCM data is clocked in on PCM IN on eight
								consecutive negative transitions of the receive data clock, which is
								CLKR in fixed-data-rate timing and DCLKR in variable-data-rate
								timing.
	PCM OUT			13	16	11	O	Transmit PCM output. PCM data is clocked out on PCM OUT on eight
								consecutive positive transitions of the transmit data clock, which is
								CLKX in fixed-data-rate timing and DCLKX in variable-data-rate
								timing.
				5	5	4	I	Power-down select. The device is inactive with a TTL low-level input
	PDN
								to this PDN and active with a TTL high-level input to this PDN.
	PWRO +			2	2	2	O	Noninverting output of power amplifier. PWRO + drives transformer
								hybrids or high-impedance loads directly in either a differential or a
								single-ended configuration.
	PWRO ±			3	3	3	O	Inverting output of power amplifier. PWRO ± is functionally identical
								with and complementary to PWRO +.
	SIGR				8		O	Signaling bit output, receive channel. In the fixed-data-rate mode,
								SIGR outputs the logical state of the 8th bit (LSB) of the PCM word
								in the most recent signaling frame.
	SIGX/ASEL			15	18		I	A-law and μ-law operation select. When connected to VBB, A-law is
								selected. When connected to VCC or GND, μ-law is selected. When
								not connected to VBB, it is a TTL-level input that is transmitted as the
								eighth bit (LBS) of the PCM word during signaling frames on PCM
								OUT (TCM29C14A and TCM129C14A only). SIGX/ASEL is
								internally connected to provide μ-law operational for TCM29C16A
								and TCM129C16A and A-law operation for TCM29C17A and
								TCM129C17A.
				14	17	12	I/O	Transmit channel time-slot strobe (output) or data clock (input) for the
	TSX/DCLKX
								transmit channel. In the fixed-data-rate mode, TSX/DCLKX is an
								open-drain output to be used as an enable signal for a 3-state output
								buffer. In the variable-data-rate mode, DCLKX becomes the transmit
								data clock, which operates at a TTL level from 64 kHz to 2.048 MHz.
	VBB			1	1	1		Most negative supply voltage. Input is ± 5 V ± 5%.
	VCC			20	24	16		Most positive supply voltage. Input is 5 V ± 5%.

4	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,

TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A

COMBINED SINGLE-CHIP PCM CODEC AND FILTER

SCTS030E ± AUGUST 1989 ± REVISED OCTOBER 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)²

Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. ±0.3 V to 15 V
Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. ±0.3 V to 15 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. ±0.3 V to 15 V
Digital ground voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±0.3 V to 15 V
Continuous total dissipation at (or below) 25°C free-air temperature . . . . . . . . . . . . . . . . . . . . .	. . . . 1375 mW
Operating free-air temperature range, TA: TCM29CxxA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . 0°C to 70°C
TCM129CxxA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package . . . . . . .	. . . . . . . 260°C

²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: Voltage values for maximum ratings are with respect to VBB.

recommended operating conditions (see Note 2)

			MIN	NOM	MAX	UNIT
VCC	Supply voltage (see Note 3)		4.75	5	5.25	V
VBB	Supply voltage		± 4.75	± 5	± 5.25	V
	Digital ground voltage, with respect to ANLG GND			0		V
VIH	High-level input voltage, all inputs except CLKSEL		2.2			V
VIL	Low-level input voltage, all inputs except CLKSEL				0.8	V
		2.048 MHz	VBB		VBB +0.5
VI	CLKSEL input voltage	1.544 MHz	0		0.5	V
		1.536 MHz	VCC ± 0.5		VCC
RL	Load resistance	GSX	10			kΩ
		PWRO + and/or PWRO ±	300			Ω
CL	Load capacitance	GSX			50	pF
		PWRO + and/or PWRO ±			100
TA	Operating free-air temperature	TCM29CxxA	0		70	°C
		TCM129CxxA	± 40		85

NOTES: 2. To avoid possible damage to these CMOS devices and resulting reliability problems, the power-up procedure described in the device power-up sequence paragraphs later in this document should be followed.

3.Voltage is at analog inputs and outputs. VCC and VBB terminals are with respect to ANLG GND. All other voltages are referenced to DGTL GND unless otherwise noted.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

5

TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,

TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A

COMBINED SINGLE-CHIP PCM CODEC AND FILTER

SCTS030E ± AUGUST 1989 ± REVISED OCTOBER 1996

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

supply current, fDCLK = 2.048 MHz, outputs not loaded

PARAMETER

TEST CONDITIONS

TCM29CxxA

TCM129CxxA

UNIT

MIN

TYP²

MAX

MIN TYP²

MAX

Supply current

Operating

7

9

8

13

ICC

Standby

FSX or FSR at VIL after 300 ms

0.5

1.1

0.7

1.5

mA

from VCC

Power down

0.3

0.9

0.4

1

PDN VIL after 300 ms

Supply current

Operating

± 7

± 9

± 8

± 13

IBB

Standby

FSX or FSR at VIL after 300 ms

± 0.5

± 1

± 0.7

± 1.5

mA

from VBB

Power down

± 0.3

± 0.9

± 0.4

± 1.1

PDN VIL after 300 ms

Operating

70

90

80

130

PD

Power dissipation

mW

Standby

FSX or FSR at VIL after 300 ms

5

10

7

15

Power down

VIL after 300 ms

3

8

4

10

PDN

² All typical values are at V

BB

= ± 5 V, V = 5 V, and T = 25°C.

CC

A

ground terminals

PARAMETER	TEST CONDITIONS	MIN TYP	MAX	UNIT
DC resistance between ANLG GND and DGTL GND		34		Ω

digital interface

	PARAMETER		TEST CONDI-	TCM29CxxA		TCM129CxxA		UNIT
			TIONS	MIN TYP²	MAX	MIN TYP²	MAX
VOH	High-level output voltage	PCM OUT	IOH = ± 9.6 mA	2.4		2.4		V
		SIGR	IOH = ± 1.2 mA	2.4		2.4
VOL	Low-level output voltage at PCM OUT, TSX,		IOL = 3.2 mA		0.4		0.5	V
	SIGR
IIH	High-level input current, any digital input		VI = 2.2 V to VCC		10		12	μA
IIL	Low-level input current, any digital input		VI = 0 to 0.8 V		10		12	μA
Ci	Input capacitance			5	10	5	10	pF
Co	Output capacitance			5		5		pF

² All typical values are at VBB = ± 5 V, VCC = 5 V, and TA = 25°C.

transmit amplifier input

PARAMETER					TEST CONDITIONS	MIN TYP² MAX	UNIT
Input current at ANLG IN +, ANLG IN ±						± 100	nA
Input offset voltage at ANLG IN +, ANLG IN ±					VI = ± 2.17 V to 2.17 V	± 25	mV
Common-mode rejection at ANLG IN +, ANLG IN ±						55	dB
Open-loop voltage amplification at GSX						5000
Open-loop unity-gain bandwidth at GSX						1	MHz
Input resistance at ANLG IN +, ANLG IN ±						10	MΩ
² All typical values are at V	BB	= ± 5 V, V	= 5 V, and T	= 25°C.
		CC	A

receive filter output

	PARAMETER					TEST CONDITIONS	MIN TYP²	MAX	UNIT
	Output offset voltage at PWRO+, PWRO ± (single ended)					Relative to ANLG GND	80	180	mV
	Output resistance at PWRO+, PWRO ±						1		Ω
	² All typical values are at V	BB	= ± 5 V, V	= 5 V, and T = 25°C.
			CC	A

6	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,

TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A

COMBINED SINGLE-CHIP PCM CODEC AND FILTER

SCTS030E ± AUGUST 1989 ± REVISED OCTOBER 1996

gain and dynamic range, VCC = 5 V, VBB = 5 V, TA = 25°C (see Notes 4, 5, and 6)

(unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN TYP	MAX	UNIT
Encoder milliwatt response (transmit gain tolerance)		Signal input = 1.064 Vrms for μ-law,	± 0.04	± 0.2	dBm0
		Signal input = 1.068 Vrms for A-law
Encoder milliwatt response (nominal supplies and temperature)		TA = 0°C to 70°C, Supplies = ± 5%		± 0.08	dB
Digital milliwatt response (receive tolerance gain) relative to		Signal input per CCITT G.711,	± 0.04	± 0.2	dBm0
zero-transmission level point		Output signal = 1 kHz
Digital milliwatt response variation with temperature and supplies		TA = 0°C to 70°C, Supplies = ± 5%		± 0.08	dB
	μ-law	RL = 600 Ω	2.76
Zero-transmission-level point, transmit channel (0 dBm0)	A-law		2.79		dBm
	μ-law	RL = 900 Ω	1
	A-law		1.03
	μ-law	RL = 600 Ω	5.76
Zero-transmission-level point, receive channel (0 dBm0)	A-law		5.79		dBm
	μ-law	RL = 900 Ω	4
	A-law		4.03

NOTES: 4. Unless otherwise noted, the analog input is a 0-dBm0, 1020-Hz sine wave, where 0 dBm0 is defined as the zero-reference point of the channel under test. This corresponds to an analog signal input of 1.064 Vrms or an output of 1.503 Vrms.

5.The input amplifier is set for noninverting unity gain. The digital input is a PCM bit stream generated by passing a 0-dBm0, 1020-Hz sine wave through an ideal encoder.

6.Receive output is measured single ended in the maximum-gain configuration. To set the output amplifier for maximum gain, GSR is connected to PWRO ± and the output is taken at PWRO +. All output levels are (sin x)/x corrected.

gain tracking over recommended ranges of supply voltage and operating free-air temperature, reference level = ±10 dBm0

PARAMETER		TEST CONDITIONS		MIN MAX	UNIT
	3	≥ input level ≥	± 40 dBm0	± 0.25
Transmit gain-tracking error, sinusoidal input	± 40 > input level ≥		± 50 dBm0	± 0.5	dB
	± 50 > input level ≥		± 55 dBm0	± 1.2
	3	≥ input level ≥	± 40 dBm0	± 0.25
Receive gain-tracking error, sinusoidal input	± 40 > input level ≥		± 50 dBm0	± 0.5	dB
	± 50	> input level ≥	± 55 dBm0	± 1.2

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

7

TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,

TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A

COMBINED SINGLE-CHIP PCM CODEC AND FILTER

SCTS030E ± AUGUST 1989 ± REVISED OCTOBER 1996

noise over recommended ranges of supply voltage and operating free-air temperature range

PARAMETER	TEST CONDITIONS		MIN TYP²	MAX	UNIT
Transmit noise, C-message weighted³	ANLG IN+ = ANLG GND,	ANLG IN ± = GSX	1	7	dBrnC0
Transmit noise, C-message weighted with 8-bit	ANLG IN+ = ANLG GND,	ANLG IN ± = GSX,		13	dBrnC0
signaling (TCM129C14A and TCM29C14A only)	6th frame signaling
Transmit noise, psophometrically weighted³	ANLG IN+ = ANLG GND,	ANLG IN ± = GSX	± 82	± 80	dBm0p
	PCM IN = 11111111 (μ-law),
Receive noise, C-message-weighted quiet code	PCM IN = 10101010 (A-law),		2	5	dBrnC0
	Measured at PWRO +
Receive noise, C-message-weighted sign bit toggled	Input to PCM IN is zero code with sign bit		3	6	dBrnC0
	toggled at 1-kHz rate
Receive noise, psophometrically weighted	PCM = lowest positive decode level			± 81	dBm0p

² All typical values are at VBB = ± 5 V, VCC = 5 V, and TA = 25°C.

³This parameter is achieved through the use of patented circuitry and is not recommended for applications in which composite signals on the transmit side are below ±55 dBm0.

power supply rejection ratio and crosstalk attenuation over recommended ranges of supply voltage and operating free-air temperature

	PARAMETER			TEST CONDITIONS		MIN TYP² MAX	UNIT
	VCC supply-voltage rejection ratio,	0 ≤ f < 30 kHz		Idle channel,		±40
				Supply signal = 200 mV(peak-to-peak),			dB
	transmit channel	30	≤ f < 50 kHz			±45
				f measured at PCM OUT
	VBB supply-voltage rejection ratio,	0 ≤ f < 30 kHz		Idle channel,		±35
				Supply signal = 200 mV(peak-to-peak),			dB
	transmit channel	30	≤ f < 50 kHz			±55
				f measured at PCM OUT
	VCC supply-voltage rejection ratio,	0 ≤ f < 30 kHz		Idle channel,		±40
				Supply signal = 200 mV(peak-to-peak),			dB
	receive channel (single ended)	30	≤ f < 50 kHz			±45
				f measured at PWRO +
	VBB supply-voltage rejection ratio,	0 ≤ f < 30 kHz		Idle channel,		±40
				Supply signal = 200 mV(peak-to-peak),			dB
	receive channel (single ended)	30	≤ f < 50 kHz			±45
				Narrow-band f measured at PWRO +
				ANLG IN+ = 0 dBm0,
	Crosstalk attenuation, transmit to receive (single ended)			f = 1.02 kHz,	Unity gain,	75	dB
				PCM IN = lowest decode level,
				Measured at PWRO +
	Crosstalk attenuation, receive to transmit (single ended)			PCM IN = 0 dBm0,	f = 1.02 kHz,	75	dB
				Measured at PCM OUT

² All typical values are at VBB = ± 5 V, VCC = 5 V, and TA = 25°C.

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