TC213 1024- ×512-PIXEL CCD IMAGE SENSOR
SOCS013B ± AUGUST 1989 ± REVISED DECEMBER 1991
• High-Resolution, Solid-State |
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DUAL-IN-LINE PACKAGE |
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Frame-Transfer Image Sensor |
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(TOP VIEW) |
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• 13.5-mm Image-Area Diagonal |
OUT1 |
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1 |
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24 |
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ABGS |
• 1000 (H) × 510 (V) Active Elements in |
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AMP GND |
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2 |
23 |
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SAG |
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Image-Sensing Area |
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• Square Pixels |
OUT2 |
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3 |
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22 |
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ABGI |
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• Low Dark Current |
ADB |
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21 |
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IAG |
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• Electron-Hole Recombination Antiblooming |
SUB |
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SUB |
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• Dynamic Range . . . More Than 60 dB |
RST2 |
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6 |
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19 |
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TDB |
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• High Sensitivity |
RST1 |
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7 |
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18 |
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SUB |
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• High Photoresponse Uniformity |
CDB |
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8 |
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SUB |
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• High Blue Response |
SRG1 |
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9 |
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16 |
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IAG |
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• Single-Phase Clocking |
SRG2 |
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10 |
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15 |
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ABGI |
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• Solid-State Reliability With No Image |
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TRG |
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14 |
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SAG |
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Burn-in, Residual Imaging, Image |
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IDB |
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12 |
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13 |
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ABGS |
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Distortion, Image Lag, or Microphonics |
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description
The TC213 is a frame-transfer charge-coupled device (CCD) image sensor that provides very high-resolution image acquisition for image-processing applications such as robotic vision, medical X-ray analysis, and metrology. The image format measures 12.00 mm horizontally by 6.12 mm vertically; the image-area diagonal is 13.5 mm. The image-area pixels are 12-mm square. The image area contains 510 active lines with 1000 active pixels per line. Two additional dark reference lines give a total of 512 lines in the image area, and 24 additional dark-reference pixels per line give a total of 1024 pixels per horizontal line.
The storage section of the TC213 contains 512 lines with 1024 pixels per line. This area is protected from exposure to light by an aluminum light shield. Photoelectric charge that is generated in the image area of the TC213 can be transferred into the storage section in less than 500 ms. After image capture (integration time), the readout is accomplished by transferring the charge, one line at a time, into two serial registers located below the storage area, each of which contains 512 data elements and 12 dummy elements. One serial-register clocks out charge that is generated in the odd-numbered columns of pixels in the imaging area; the other serial-register processes charge from the even-numbered columns of the imaging area. The typical serial-register data rate is 10 megapixels per second. Three transfer gates are used to isolate the serial registers. If the storage area or storage and image areas need to be cleared of all charge, charge may be quickly transferred across the serial registers and into the clearing drain, which is located below the serial-register section.
This MOS device contains limited built-in gate protection. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to SUB. Under no circumstances should pin voltages exceed absolute maximum ratings. Avoid shorting OUTn to ADB during operation to prevent damage to the amplifier. The device can also be damaged if the output terminals are reverse-biased and an excessive current is
allowed to flow. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 1991, Texas Instruments Incorporated
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
2-1 |
TC213
1024- ×512-PIXEL CCD IMAGE SENSOR
SOCS013B ± AUGUST 1989 ± REVISED DECEMBER 1991
description (continued)
Gated floating-diffusion detection structures are used with each serial register to convert charge to signal voltage. External resets allow the application of off-chip correlated clamp sample-and-hold amplifiers for low-noise performance. To provide high output-drive capability, both outputs are buffered by low-noise, two-stage, source-follower amplifiers. These two output signals can provide a data rate of 20 megapixels per second when combined off chip. An output of 30 frames per second with one field per frame is typical. At room temperature, the readout noise is 55 elecrons and a minimum dynamic range of 60 dB is available.
The blooming protection incorporated into the sensor is based on recombining excess charge with charge of opposite polarity in the substrate. This antiblooming is activated by supplying clocking pulses to the antiblooming gate, which is an integral part of each image-sensing element. The storage area antiblooming gate is clocked only for charge transfer in normal use.
The TC213 is built using TI-proprietary virtual-phase technology, which provides devices with high blue response, low dark signal, good uniformity, and single-phase clocking.
The TC213 is characterized for operation from ±10°C to 40°C.
functional block diagram
Top Drain
TDB |
19 |
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IAG |
21 |
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22 |
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ABGI |
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SAG |
23 |
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24 |
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ABGS |
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4 |
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ADB |
Amplifiers |
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6 |
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RST2 |
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OUT2 |
3 |
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RST1 |
7 |
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OUT1 |
1 |
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12 Dummy |
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Elements |
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2 |
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AMP GND
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16 |
Image Area With |
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IAG |
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15 |
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Blooming Protection |
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24 Dark Reference Elements |
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ABGI |
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14 |
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SAG |
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13 |
Storage Area |
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ABGS |
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IDB |
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12 |
10 |
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SRG2 |
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9 |
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SRG1 |
Multiplexer, Transfer Gates, |
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and Serial Registers |
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11 |
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TRG |
Clearing Drain |
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8 |
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CDB |
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2-2 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
TC213 1024- ×512-PIXEL CCD IMAGE SENSOR
SOCS013B ± AUGUST 1989 ± REVISED DECEMBER 1991
sensor topology diagram
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1000 Pixels |
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510 Lines |
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22 Pixels |
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1 Pixel |
1 Pixel |
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2 Lines |
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512 Lines
Dummy Pixels
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12 |
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511 |
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12 |
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511 |
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Terminal Functions
TERMINAL |
I/O |
DESCRIPTION |
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NAME |
NO. |
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ABGI² |
15 |
I |
Antiblooming gate for image area |
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ABGI² |
22 |
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Antiblooming gate for image area |
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ABGS² |
13 |
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Antiblooming gate for storage area |
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ABGS² |
24 |
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Antiblooming gate for storage area |
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ADB |
4 |
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Supply voltage for amplifier drain bias |
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AMP GND |
2 |
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Amplifier ground |
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CDB |
8 |
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Supply voltage for clearing drain bias |
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IAG² |
16 |
I |
Image-area gate |
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IAG² |
21 |
I |
Image-area gate |
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IDB |
12 |
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Supply voltage for input diode bias |
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OUT1 |
1 |
O |
Output signal 1 |
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OUT2 |
3 |
O |
Output signal 2 |
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RST1 |
7 |
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Reset gate 1 |
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RST2 |
6 |
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Reset gate 2 |
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SAG² |
14 |
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Storage-area gate |
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SAG² |
23 |
I |
Storage-area gate |
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SRG1 |
9 |
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Serial-register gate 1 |
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SRG2 |
10 |
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Serial-register gate 2 |
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SUB² |
5 |
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Substrate and clock return |
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SUB² |
17 |
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Substrate and clock return |
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SUB² |
18 |
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Substrate and clock return |
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SUB² |
20 |
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Substrate and clock return |
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TDB |
19 |
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Supply voltage for top drain bias |
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TRG |
11 |
I |
Transfer gate |
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²All pins of the same name should be connected together externally (i.e., pin 15 to pin 22, pin 13 to pin 24, etc.).
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
2-3 |
TC213
1024- ×512-PIXEL CCD IMAGE SENSOR
SOCS013B ± AUGUST 1989 ± REVISED DECEMBER 1991
detailed description
The TC213 consists of four basic functional blocks: (1) the image-sensing area, (2) the image-storage area,
(3) the multiplexer block with serial registers and transfer gates, and (4) the low-noise signal-processing amplifier block with charge-detection nodes. The location of each of these blocks is identified in the functional block diagram.
image-sensing and image-storage areas
Figures 1 and 2 show cross sections with potential well diagrams and top views of image-sensing elements. As light enters the silicon in the image-sensing area, free electrons are generated and collected in the potential wells of the sensing elements. During this time, blooming protection is activated by applying a burst of pulses to the antiblooming gate inputs every horizontal blanking interval. This prevents blooming caused by the spilling of charge from overexposed elements into neighboring elements. After integration is complete, the signal charge is transferred into the storage area (see Figure 5).
There are 24 full columns of elements at the left edge of the image-sensing area that are shielded from incident light; these elements provide the dark reference used in subsequent video-processing circuits to restore the video black level. There are also two dark lines at the bottom of the image-sensing area that prevent charge leakage from the image-sensing area into the image-storage area.
multiplexer with transfer gates and serial registers
The multiplexer and transfer gates transfer charge line by line from the image-storage area columns into the corresponding serial registers and prepare it for readout. Figure 3 illustrates the layout of the multiplexing gate that vertically separates the pixels for input into the serial registers. Figure 4 shows the layout of the interface region between the serial-register gates and the transfer gates. Multiplexing is activated during the horizontal blanking interval by applying appropriate pulses to the transfer gates and serial registers; the required pulse timing is shown in Figure 6. A drain is also included to provide the capability to clear the image-sensing area of unwanted charge. Such charge can accumulate in the imager during the start-up of operation or under special circumstances when nonstandard timing is desired. The clear timing is given as part of the parallel-transfer timing in Figure 5.
serial-register readout and video processing
After transfer into the serial registers, the pixels are normally read out 180° out of phase (see Figure 7). Each serial register must be reset to the reference level before the next pixel is read out. The timing for the resets and their relationships to the serial-register pulses is shown in Figure 8. Figure 8 also shows the timing for the pixel clamp and sample and hold needed for an off-chip double-correlated sampling circuit. These two output signals can provide a data rate of 20 million pixels per second when combined off chip. After the charge is placed on the detection node, it is buffered and amplified by a low-noise, dual-stage source follower. Each serial register contains 12 dummy elements that are used to span the distance between the serial register and the output amplifier. A schematic is shown in Figure 9. The location of the dummy elements, which are considered to be part of the amplifiers, is shown in the functional block diagram. Figure 10 gives the timing for a single frame of video. An output of 30 frames per second with one field per frame is typical.
2-4 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
TC213 1024- ×512-PIXEL CCD IMAGE SENSOR
SOCS013B ± AUGUST 1989 ± REVISED DECEMBER 1991
μ |
Clocked Barrier |
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Light |
12 m(H) |
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φ-IAG |
φ-ABG |
12 μm(V) |
Virtual Barrier |
Antiblooming |
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Antiblooming Gate |
Clocking Levels |
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Virtual Well |
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Clocked Well |
Accumulated Charge |
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Figure 1. Charge-Accumulation Process
φ-PS
Clocked Phase
Virtual Phase
Channel Stops
Figure 2. Charge-Transfer Process
Channel Stops
Channel |
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Serial- |
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Register |
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Stop |
Clocked |
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Gate |
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Virtual |
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Wells |
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Well |
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Clocked |
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Well Multiplexing |
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Gate |
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Transfer
Gate
Figure 3. Multiplexing-Gate Layout |
Figure 4. Interface-Region Layout |
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POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
2-5 |
TC213
1024- ×512-PIXEL CCD IMAGE SENSOR
SOCS013B ± AUGUST 1989 ± REVISED DECEMBER 1991
1 μs |
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Line 1 |
Line 2 |
Line 511 Line 512 |
IAG |
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SAG |
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Intermediate |
High |
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ABGI |
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Low |
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Intermediate |
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ABGS |
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TRG
SRG1²
SRG2²
RST1
High
RST2
High
²SRG1 and SRG2 pulses are extended to equal TRG and SAG pulse widths during parallel transfers from the storage area to the clearing drain.
Figure 5. Parallel-Transfer Timing
2-6 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
TC213 1024- ×512-PIXEL CCD IMAGE SENSOR
SOCS013B ± AUGUST 1989 ± REVISED DECEMBER 1991
CSYNC
CBLNK
TRG
SRG1²
SRG2²
RST1 High
RST2 High
CL1 Low
CL2 Low
SH1 Low
SH2 Low
SAG
ABGS |
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Intermediate |
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ABGI
CPOB1
CPOB2
IAG Low
² SRG1 and SRG2 pulses are extended to equal TRG and SAG pulse widths during horizontal line transfer operation for readout.
Figure 6. Horizontal Timing
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
2-7 |
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