Texas Instruments SN54AS161J, SN74ALS163BD, SN74ALS163BDR, SN74ALS163BN, SN74ALS163BN3 Datasheet

SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163 SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS

SDAS276 ± DECEMBER 1994

• Internal Look-Ahead Circuitry for Fast

SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161,

Counting

SN54AS163 . . . J PACKAGE

• Carry Output for n-Bit Cascading

SN74ALS161B, SN74ALS163B, SN74AS161,

SN74AS163 . . . D OR N PACKAGE

• Synchronous Counting

(TOP VIEW)

• Synchronously Programmable

CLR

1

16

VCC

• Package Options Include Plastic

CLK

2

15

RCO

Small-Outline (D) Packages, Ceramic Chip

A

3

14

QA

Carriers (FK), and Standard Plastic (N) and

B

4

13

QB

Ceramic (J) 300-mil DIPs

C

5

12

QC

description

D

6

11

QD

ENP

7

10

ENT

These synchronous, presettable, 4-bit decade

GND

8

9

LOAD

and binary counters feature an internal carry

look-ahead circuitry for application in high-speed

SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161,

counting designs. The SN54ALS162B is a 4-bit

SN54AS163 . . . FK PACKAGE

decade

counter.

The

′ALS161B,

′ALS163B,

(TOP VIEW)

′AS161, and ′AS163 are 4-bit binary counters.

CLK

CLR

NC

V

RCO

Synchronous operation is provided by having all

CC

flip-flops clocked simultaneously so that the

outputs change coincidentally with each other

A

3

2

1

20 19

QA

when instructed by the count-enable (ENP, ENT)

4

18

inputs and internal gating. This mode of operation

B

5

17

QB

eliminates the output counting spikes normally

NC

6

16

NC

associated with asynchronous (ripple-clock)

C

7

15

QC

counters. A buffered clock (CLK) input triggers the

D

8

9

14

QD

four flip-flops on the rising (positive-going) edge of

10 11 12 13

the clock input waveform.

ENP

GND

NC

LOAD

ENT

These counters are fully programmable; they may

be preset to any number between 0 and 9 or 15.

NC ± No internal connection

Because presetting is synchronous, setting up a

low level at the load (LOAD) input disables the

counter and causes the outputs to agree with the

setup data after the next clock pulse, regardless of

the levels of the enable inputs.

The clear function for the ′ALS161B and ′AS161 is asynchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low, regardless of the levels of the CLK, LOAD, or enable inputs. The clear function for the SN54ALS162B, ′ALS163B, and ′AS163 is synchronous, and a low level at CLR sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to CLR to synchronously clear the counter to 0000 (LLLL).

The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. ENP and ENT inputs and a ripple-carry (RCO) output are instrumental in accomplishing this function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled, produces a high-level pulse while the count is maximum (9 or 15 with QA high). The high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1994, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163 SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS

SDAS276 ± DECEMBER 1994

description (continued)

These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times.

The SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, and SN54AS163 are characterized for operation over the full military temperature range of ±55°C to 125°C. The SN74ALS161B, SN74ALS163B, SN74AS161, and SN74AS163 are characterized for operation from 0°C to 70°C.

logic symbols²

′ALS161B AND ′AS161 BINARY COUNTERS

′ALS163B AND ′AS163 BINARY COUNTERS

WITH DIRECT CLEAR

WITH SYNCHRONOUS CLEAR

1

CTRDIV16

1

CTRDIV16

CT=0

5CT=0

CLR

CLR

9

9

M1

M1

LOAD

15

LOAD

15

10

M2

3CT=15

RCO

10

M2

3CT=15

RCO

ENT

G3

ENT

G3

7

7

ENP

G4

ENP

G4

2

2

CLK

C5/2,3,4+

14

CLK

C5/2,3,4+

14

3

3

A

1, 5D [1]

QA

A

1, 5D [1]

QA

4

13

QB

4

13

QB

B

[2]

B

[2]

5

12

QC

5

12

QC

[4]

[4]

C

C

6

11

QD

6

11

QD

D

[8]

D

[8]

SN54ALS162B DECADE COUNTER

WITH SYNCHRONOUS CLEAR

1

CTRDIV10

5CT=0

CLR

9

M1

LOAD

15

10

M2

3CT=9

RCO

ENT

G3

7

ENP

G4

2

CLK

C5/2,3,4+

3

14

QA

A

1, 5D

[1]

4

13

QB

[2]

B

5

12

QC

[4]

C

6

11

QD

[8]

D

² These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages.

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163 SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS

	SDAS276 ± DECEMBER 1994
logic diagram (positive logic)
9	SN54ALS162B
LOAD
10		15
ENT
7		RCO
ENP
1
CLR
2
CLK
	C1	14
		QA
	1D
3
A
		13
	C1	QB
	1D
4
B
		12
	C1	QC
	1D
5
C
		11
	C1	QD
	1D
6
D

Pin numbers shown are for the J package.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

3

SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163 SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS

SDAS276 ± DECEMBER 1994

	logic diagram (positive logic)
	′ALS163B and ′AS163
	1
	CLR
	9
	LOAD
	10
	ENT	15
	7
		RCO
	ENP
	2
	CLK
	C1	14
		QA
	1D
	3
	A
	C1	13
		QB
	1D
	4
	B
	C1	12
		QC
	1D
	5
	C
	C1	11
		QD
	1D
	6
	D

Pin numbers shown are for the D, J, and N packages.

′ALS161B and ′AS161 synchronous binary counters are similar; however, CLR is asynchronous.

4	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163 SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS

SDAS276 ± DECEMBER 1994

typical clear, preset, count, and inhibit sequences

SN54ALS162B

The following sequence is illustrated below:

1.Clear outputs to zero (SN54ALS162B is synchronous)

2.Preset to BCD 7

3.Count to 8, 9, 0, 1, 2, and 3

4.Inhibit

CLR

LOAD

A

B

Data

Inputs

C

D

CLK

ENP

ENT

QA

Data QB

Outputs

QC

QD

RCO

7	8	9	0	1	2	3
			Count			Inhibit
Sync Preset
Clear
Async
Clear

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