TEXAS INSTRUMENTS UC1827-1, UC1827-2, UC2827-1, UC2827-2, UC3827-1 Technical data
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UC1827
UC1827-1, UC1827-2
UC2827-1, UC2827-2
UC3827-1, UC3827-2
www.ti.com |
SLUS365A –APRIL 1999 –REVISED AUGUST 2005 |
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BUCK CURRENT/VOLTAGE FED PUSH-PULL
PWM CONTROLLERS
FEATURES
∙Ideal for Multiple Output and/or High Voltage Output Voltage Converters
∙Up to 500 kHz Operation
∙High Voltage, High Current Floating Driver for Buck Converter Stage
∙UC3827-1 Current Fed Controller has Push-Pull Drivers with Overlapping Conduction Periods
∙UC3827-2 Voltage Fed Controller has Push-Pull Drivers with Nonoverlapping Conduction Periods
∙Average Current Mode, Peak Current Mode or Voltage Mode with Input Voltage Feedforward Control for Buck Power Stage
∙Wide Bandwidth, Low Offset, Differential Current Sense Amplifier
∙Precise Short Circuit Current Control
DESCRIPTION
The UC3827 family of controller devices provides an integrated control solution for cascaded buck and push-pull converters. These converters are known as current fed or voltage fed push-pull converters and are ideally suited for multiple output and/or high voltage output applications. In both current fed and voltage fed modes, the push-pull switches are driven at 50% nominal duty cycles and at one half the switching frequency of the buck stage. In the current fed mode, the two switches are driven with a specified over-lap period to prevent ringing and voltage stress on the devices. In the voltage fed mode, the two switches are driven with a specified gap time between the switches to prevent shorting the transformer across the energy storage capacitor and to prohibit excessive currents flowing through the devices.
The converter'soutput voltage is regulated by pulse width modulation of the buck switch. The UC3827 contains complete protection and PWM control functions for the buck converter. Easy control of the floating switch is accomplished by the floating drive circuitry. The gate drive waveform is level shifted to support an input voltage up to 72 VDC.
BLOCK DIAGRAM
VEAOCEA+ CEAO RAMP
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12 |
6 |
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Voltage Error |
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VEA+ 14 |
Amplifier |
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0.7 V |
PWM Comparator |
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Current Error |
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VEA− |
16 |
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+ |
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Amplifier |
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CEA− 13 |
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CSAO 7 |
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RD |
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Flying |
1 |
V+ |
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+3 V |
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Driver |
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CSA+ |
8 |
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ILIM Comparator |
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S |
Q |
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BUCK |
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CSA− |
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Current Sense |
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3 |
SRC |
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SS |
4 |
Amplifier |
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SS |
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OSC |
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INHBT |
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SYNC 19 |
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21 |
PGND |
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UV |
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CT |
18 |
OSC |
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Q |
DELAY |
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500 kHz |
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T |
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RT 17 |
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Push/Pull |
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MAX |
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Q |
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Drivers |
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REF 15 |
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24 |
PUSH |
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VCC 23 |
REF |
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& |
UVLO |
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DELAY |
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PULL |
GND |
11 |
UVLO |
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20 |
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DELAY |
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. |
Copyright © 1999–2005, Texas Instruments Incorporated |
Products conform to specifications per the terms of the Texas |
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Instruments standard warranty. Production processing does not |
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necessarily include testing of all parameters. |
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UC1827-1, UC1827-2
UC2827-1, UC2827-2
UC3827-1, UC3827-2
www.ti.com
SLUS365A –APRIL 1999 –REVISED AUGUST 2005
DESCRIPTION (CONTINUED)
The UC3827 can be set up in traditional voltage mode control using input voltage feedforward technique or in current mode control. Using current mode control prevents potential core saturation of the push-pull transformer due to mismatches in timing and in component tolerances. With average current mode control, precise control of the inductor current feeding the push-pull stage is possible without the noise sensitivity associated with peak current mode control. The UC3827 average current mode loop can also be connected in parallel with the voltage regulation loop to assist only in fault conditions.
Other valuable features of the UC3827 include bidirectional synchronization capability, user programmable overlap time (UC3827-1), user programmable gap time (UC3827-2), a high bandwidth differential current sense amplifier, and soft start circuitry.
ORDERING INFORMATION(1)
TA = TJ |
PUSH-PULL TOPOLOGY |
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PACKAGES |
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SOIC-24 |
PDIP-24 |
PLCC-28 |
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-55°C to 125°C |
Current Fed |
UC1827J-1 |
UC1827J-1 |
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Voltage Fed |
UC1827J-2 |
UC1827J-2 |
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-40°C to 85°C |
Current Fed |
UC2827DW-1 |
UC2827N-1 |
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Voltage Fed |
UC2827DW-2 |
UC2827N-2 |
- |
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0°C to 70°C |
Current Fed |
UC3827DW-1 |
UC3827N-1 |
UC3827Q-1 |
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Voltage Fed |
UC3827DW-2 |
UC3827N-2 |
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(1)The DW and Q packages are also available taped and reeled. Add a TR suffix to the device type (i.e., UC2827DWTR-1).
DISSIPATION RATINGS
PACKAGE |
(θJA) JUNCTION-TO-AMBIENT |
(θJC) JUNCTION-TO-WHAT? |
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TEMPERATURE (°C/W) |
TEMPERATURE (°C/W) |
24-pin (N) |
60(1) |
30 |
24-pin (J) |
70 to 90 |
28(2) |
28-pin (DW) |
71 to 83(3) |
24(3) |
28-pin (QLCC) |
40-65(1) |
30 |
(1)Specified θJA (junction-to-ambient) refers to devices mounted to 5-in2 FR4 PC board with 1 oz. copper where noted. When a resistance range is given, the lower values refer to a 5-in2 aluminum PC board. The test PWB is 0.062 inches thick and typically used 0.635 mm trace widths for power packages and 1.3 mm trace widths for non-power packages with a 100 × 100 mil probe land area at the end of each trace.
(2)Specified θJC (junction-to-what?) data values stated were derived from MIL-STD-1835B which states "The baseline values shown are worst case (mean + 2s) for a 60 x 60 mil microcircuit device silicon die and applicable for devices with die sizes up to 14400 mils2. For device sizes greater than 14400 mils2 use the following values; dual-in-line, 11 °C/W; flat pack, 10 °C/W; pin grid array, 10 °C/W pin grid array, 10 °C/W."
(3)Modeled data. If there is a value range given for θJA, the lower value refers to a 3 x 3 in., 1-oz, internal copper ground plane. The higher value refers to a 1 x 1 in. ground plane. All model data assumes only one trace for each non-fused lead.
2
UC1827-1, UC1827-2 UC2827-1, UC2827-2
UC3827-1, UC3827-2
www.ti.com
SLUS365A –APRIL 1999 –REVISED AUGUST 2005
ABSOLUTE MAXIMUM RATINGS(1)
Supply voltage, VCC
Input voltage range
BUCK driver
PUSH/PULL driver
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UC2827-1 |
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UC2827-2 |
UNITS |
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UC3827-1 |
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UC3827-2 |
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20 |
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CEAO, CEA+, CEA-, CSAO, CSA+, CSA-, CT, DELAY, PUSH, PULL, |
–0.3 to 5 |
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RAMP, RT, SS, SYNC, VEA+, VEAO, |
V |
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V+ and BUCK |
90 |
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SRC |
90-VCC |
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I/O continuous |
±250 |
mA |
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I/O peak |
±1 |
A |
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I/O continuous |
±200 |
mA |
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I/O peak |
±0.8 |
A |
Storage temperature |
–65 to 150 |
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Junction temperature |
–55 to 150 |
°C |
Lead temperature (soldering, 10 sec) |
300 |
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(1)Voltages are referenced to ground. Currents are positive into, negative out of the specified terminal. Consult Packaging section of databook for thermal limitations and considerations of packages.
CONNECTION DIAGRAMS
DIL-24 (N or J, DW PACKAGES) (TOP VIEW)
N, J OR DW PACKAGES
(TOP VIEW)
V+ |
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1 |
24 |
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PUSH |
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BUCK |
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2 |
23 |
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VCC |
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SRC |
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3 |
22 |
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PULL |
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SS |
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4 |
21 |
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PGND |
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RAMP |
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5 |
20 |
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DELAY |
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CEAO |
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6 |
19 |
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SYNC |
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CSAO |
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7 |
18 |
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CT |
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CSA+ |
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8 |
17 |
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RT |
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CSA− |
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9 |
16 |
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VEA− |
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VEAO |
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10 |
15 |
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REF |
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GND |
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11 |
14 |
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VEA+ |
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CEA+ |
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12 |
13 |
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CEA− |
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PLCC-28 (Q PACKAGE)
(TOP VIEW)
Q PACKAGE (TOP VIEW)
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SRC |
BUCK |
NC |
V+ |
PUSH |
VCC |
PULL |
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SS |
4 |
3 |
2 |
1 |
28 27 26 |
PGND |
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5 |
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25 |
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RAMP |
6 |
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24 |
NC |
CEAO |
7 |
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23 |
NC |
CSAO |
8 |
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22 |
DELAY |
CSA+ |
9 |
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21 |
SYNC |
CSA− |
10 |
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20 |
CT |
VEAO |
11 |
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19 |
RT |
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12 13 14 15 16 17 18 |
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GND |
CEA+ |
CEA− |
VEA+ |
REF |
NC |
VEA− |
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NC − No internal connection
3
UC1827-1, UC1827-2
UC2827-1, UC2827-2
UC3827-1, UC3827-2
www.ti.com
SLUS365A –APRIL 1999 –REVISED AUGUST 2005
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Terminal Functions |
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TERMINAL |
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NAME |
N or |
Q |
I/O |
DESCRIPTION |
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DW |
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Output of the buck PWM controller. The BUCK output is a floating driver, optimized for controlling the |
BUCK |
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2 |
3 |
O |
gate of an N-channel MOSFET. The peak sink and source currents are 1 A. VCC undervoltage faults |
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disables BUCK to an off condition (low). |
CEA+ |
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12 |
13 |
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Non-inverting input of the current error amplifier. |
CEA- |
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13 |
14 |
I |
Inverting input of the current error amplifier |
CEAO |
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6 |
7 |
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Output of the current error amplifier and the inverting input of the PWM comparator of the buck |
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converter. |
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CSA+ |
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8 |
9 |
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Noninverting input of the current sense amplifier. |
CSA– |
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9 |
10 |
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Inverting input of the current sense amplifier. |
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Output of the current sense amplifier and the noninverting input of the current limit comparator. When |
CSAO |
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7 |
8 |
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the signal level on this pin exceeds the 3V threshold of the current limit comparator, the buck gate drive |
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pulse is terminated. This feature is useful to implement cycle-by-cycle current limiting for the buck |
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converter. |
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Provides for the timing capacitor which is connected between CT and GND. The oscillator frequency is |
CT |
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18 |
20 |
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set by CT and a resistor RT, connected between pin RT and GND. The CT discharge current is |
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approximately 40 x the bias current through the resistor connected to RT. A practical maximum value for |
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the discharge current is 20 mA. The frequency of the oscillator is given by equation(1) |
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A resistor to GND programs the overlap time of the PUSH and PULL outputs of the UC3827-1 and the |
DELAY |
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20 |
22 |
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dead time of the PUSH and PULL outputs of the UC3827-2. The minimum value of the resistor, RDELAY, |
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is 18 kΩ. The delay or overlap time is given by equation(2) |
GND |
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11 |
12 |
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Ground reference for all sensitive setup components not related to driving the outputs. They include all |
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timing, voltage sense, current sense, and bypass components. |
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Ground connection for the PUSH and PULL outputs. PGND must be connected to GND at a single point |
PGND |
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21 |
25 |
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on the printed circuit board. This is imperative to prevent large, high frequency switching currents |
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flowing through the ground metalization inside the device. |
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Ground referenced output to drive an N-channel MOSFET. The PULL and the PUSH outputs are driving |
PULL |
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22 |
26 |
O |
the two switches of the push-pull converter with complementary signals at close to a 50% duty cycle. |
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Any undervoltage faults will disable PULL to an off condition (low). |
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Ground referenced output to drive an N-channel MOSFET. The PULL and the PUSH outputs are driving |
PUSH |
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24 |
28 |
O |
the two switches of the push-pull converter with complementary signals at close to a 50% duty cycle. |
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Any undervoltage faults disables PUSH to an off condition (low). |
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The RAMP voltage, after a 700 mV internal level shift, is fed to the noninverting input of the buck PWM |
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comparator. A resistor to VIN and a capacitor to GND provide an input voltage feedforward signal for the |
RAMP |
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5 |
6 |
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buck controller in voltage mode control. In peak current mode control, the RAMP pin receives the |
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current signal of the buck converter. In an average current mode setup, the RAMP pin has a linearly |
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increasing ramp signal. This waveform may be generated either by connecting RAMP directly to CT, or |
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by connecting both a resistor from VCC to RAMP and a capacitor from RAMP to GND. |
REF |
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15 |
16 |
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The output of the +5V on board reference. Bypass this pin with a capacitor to GND. The reference is off |
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when the chip is in undervoltage lockout mode.o |
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A resistor to GND programs the charge current of the timing capacitor connected to CT. The charge |
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current approximately equals that shown in equation(3). The charge current should be less than 500 µA |
RT |
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17 |
19 |
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to keep CT'sdischarge peak current less than 20 mA, which is CT'smaximum practical discharge value. |
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The discharge time, which sets the maximum duty cycle, is set internally and is influenced by the charge |
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current. |
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The source connection for the floating buck switch. The voltage on the SRC pin can exceed VCC but |
SRC |
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3 |
4 |
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must be lower than 90 V–VVCC. Also, during turn-off transients of the buck switch, the voltage at SRC |
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can go to –2V. |
f |
OSC |
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0.77 |
(Hz) |
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(1) |
RRT |
CCT |
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tDELAY RDELAY 10 9 (s)
(2)200
2.5 V
(3) IRT RRT
4
UC1827-1, UC1827-2 UC2827-1, UC2827-2
UC3827-1, UC3827-2
www.ti.com
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SLUS365A –APRIL 1999 –REVISED AUGUST 2005 |
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Terminal Functions (continued) |
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TERMINAL |
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NAME |
N or |
Q |
I/O |
DESCRIPTION |
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DW |
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5Soft-start pin requires a capacitor to GND. During soft-start the output of the voltage error amplifier is |
SS |
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4 |
5 |
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clamped to the soft-start capacitor voltage which is slowly charged by an internal current source. In |
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UVLO, SS is held low. |
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A bidirectional pin for the oscillator., used to synchronize several chips to the fastest oscillator. Its input |
SYNC |
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19 |
21 |
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synchronization threshold is 1.4 V. The SYNC voltage is 3.6 V when the oscillator capacitor, CT, is |
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discharged. Otherwise it is 0 V. If the recommended synchronization circuit is not used, a 1 kΩ or lower |
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value resistor from SYNC to GND may be needed to increase the fall time of the signal at SYNC. |
VCC |
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23 |
27 |
I |
A voltage source connected to this pin supplies the power for the UC3827. It is recommended to bypass |
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this pin to both GND and PGND ground connections with good quality high frequency capacitors |
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VEA+ |
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14 |
15 |
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Non-inverting input of the voltage error amplifier |
VEA- |
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16 |
18 |
I |
Inverting input of the voltage error amplifier |
VEAO |
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10 |
11 |
O |
Output of the voltage error amplifier |
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Supply voltage for the buck output. The floating driver of the UC3827 uses the bootstrap technique |
V+ |
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1 |
1 |
I |
which requires a reservoir capacitor to store the required energy for the on time of the buck switch. A |
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diode must be connected from VCC to V+ to charge the reservoir capacitor. This diode must be able to |
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withstand VIN. The reservoir capacitor must be connected between V+ and SRC.
ELECTRICAL CHARACTERISTICS
Unless otherwise spsecified, VVCC = 15 V, VV+ = 14.3 V, CCT = 340 pF, RRT = 10 kΩ, RDELAY = 24.3 kΩ, VSRC = VGND = VBUCK= VPUSH = VPULL outputs no load, TJ = TA
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PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
SUPPLY |
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VCC UVLO, Turn-on |
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8.3 |
8.8 |
9.5 |
V |
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Hysteresis |
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0.9 |
1.2 |
1.5 |
V |
IVCC |
Supply current start |
VVCC = 8 V |
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1000 |
µA |
IVCC |
Supply current run |
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32 |
45 |
mA |
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IV+ buck high |
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0.2 |
1 |
2 |
mA |
VOLTAGE ERROR AMPLIFIER |
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IB |
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0.5 |
3 |
µA |
VIO |
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10 |
mV |
AVOL |
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80 |
95 |
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dB |
GBW(1) |
Gain bandwidth |
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1 |
4 |
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MHz |
VOL |
Low-level output voltage |
IVEAO = 0 µA (No load) |
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0.3 |
0.5 |
V |
VOH |
High-level output voltage |
IVEAO = 0 µA (No load) |
2.85 |
3 |
3.20 |
V |
CURRENT SENSE AMPLIFIER |
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IB |
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–1 |
–5 |
µA |
VIO |
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5 |
mV |
AVOL |
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80 |
110 |
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dB |
GBW (1) |
Gain bandwidth |
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15 |
29 |
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MHz |
VOL |
Low-level output voltage |
ICEAO = 0 µA (No load) |
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0.25 |
0.5 |
V |
VOH |
High-level output voltage |
ICEAO = 0 µA (No load) |
3 |
3.3 |
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V |
CMRR |
Common mode range(1) |
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-0.3 |
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2 |
V |
CURRENT ERROR AMPLIFIER |
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IB |
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–1 |
–5 |
µA |
VIO |
|
|
|
|
10 |
mV |
AVOL |
|
|
80 |
110 |
|
dB |
(1)Ensured by design. Not production tested.
5
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