Fairchild Semiconductor 74LVTH240WM, 74LVTH240SJX, 74LVTH240SJ, 74LVTH240MTCX, 74LVTH240MTC Datasheet

July 1999

Revised August 1999

74LVT240 • 74LVTH240

Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs

General Description

The LVT240 and LVTH240 are inverting octal buffers and line drivers designed to be employed as memory address drivers, clock drivers and bus oriented transmitters or receivers which provides improved PC board density.

The LVTH240 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs.

These octal buffers and line drivers are designed for lowvoltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT240 and LVTH240 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation.

Features

■Input and output interface capability to systems at 5V VCC

■Bushold data inputs eliminate the need for external pullup resistors to hold unused inputs (74LVTH240), also available without bushold feature (74LVT240).

■Live insertion/extraction permitted

■Power Up/Down high impedance provides glitch-free bus loading

■Outputs source/sink −32 mA/+64 mA

■Functionally compatible with the 74 series 240

■Latch-up performance exceeds 500 mA

Ordering Code:

Order Number	Package Number	Package Description
74LVT240WM	M20B	20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74LVT240SJ	M20D	20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVT240MSA	MSA20	20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74LVT240MTC	MTC20	20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LVTH240WM	M20B	20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74LVTH240SJ	M20D	20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVTH240MSA	MSA20	20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74LVTH240MTC	MTC20	20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

IEEE/IEC

Outputs STATE-3 with Driver Buffer/Line Octal Voltage Low 74LVTH240 • 74LVT240

© 1999 Fairchild Semiconductor Corporation

DS500153

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74LVT240 • 74LVTH240

Connection Diagram	Pin Descriptions
		Pin Names									Description
					1,				2		3-STATE Output
			OE				OE
											Enable Inputs
			I0–I7								Inputs
								7			3-STATE Outputs
			O	0–O

Truth Tables

		Inputs			Outputs
					(Pins 12, 14, 16, 18)
	OE1			In
	L			L	H
	L			H	L
	H			X	Z
		Inputs			Outputs
					(Pins 3, 5, 7, 9)
	OE2			In
	L			L	H
	L			H	L
	H			X	Z

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Z = High Impedance

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Absolute Maximum Ratings(Note 1)

Symbol	Parameter	Value	Conditions	Units
VCC	Supply Voltage	−0.5 to +4.6		V
VI	DC Input Voltage	−0.5 to +7.0		V
VO	DC Output Voltage	−0.5 to +7.0	Output in 3-STATE	V
		−0.5 to +7.0	Output in HIGH or LOW State (Note 2)	V
IIK	DC Input Diode Current	−50	VI < GND	mA
IOK	DC Output Diode Current	−50	VO < GND	mA
IO	DC Output Current	64	VO > VCC Output at HIGH State	mA
		128	VO > VCC Output at LOW State	mA
ICC	DC Supply Current per Supply Pin	±64		mA
IGND	DC Ground Current per Ground Pin	±128		mA
TSTG	Storage Temperature	−65 to +150		°C
Recommended Operating Conditions

Symbol	Parameter	Min	Max	Units
VCC	Supply Voltage	2.7	3.6	V
VI	Input Voltage	0	5.5	V
IOH	HIGH-Level Output Current		−32	mA
IOL	LOW-Level Output Current		64
TA	Free-Air Operating Temperature	−40	85	°C
t/ V	Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V	0	10	ns/V

Note 1: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.

Note 2: IO Absolute Maximum Rating must be observed.

DC Electrical Characteristics

				VCC	T A =-40°C to +85°C
	Symbol	Parameter						Units	Conditions
					Min	Typ	Max
				(V)
						(Note 3)
	VIK	Input Clamp Diode Voltage		2.7			-1.2	V	II = -18 mA
	VIH	Input HIGH Voltage		2.7–3.6	2.0			V	VO £ 0.1V or
	VIL	Input LOW Voltage		2.7–3.6			0.8		VO ³ VCC - 0.1V
	VOH	Output HIGH Voltage		2.7–3.6	VCC-0.2			V	IOH = -100 mA
				2.7	2.4			V	IOH = -8 mA
				3.0	2.0			V	IOH = -32 mA
	VOL	Output LOW Voltage		2.7			0.2	V	IOL = 100 mA
				2.7			0.5	V	IOL = 24 mA
				3.0			0.4	V	IOL = 16 mA
				3.0			0.5	V	IOL = 32 mA
				3.0			0.55	V	IOL = 64 mA
	II(HOLD)	Bushold Input Minimum Drive		3.0	75			mA	VI = 0.8V
	(Note 4)				-75			mA	VI = 2.0V
	II(OD)	Bushold Input Over-Drive		3.0	500			mA	(Note 5)
		Current to Change State
	(Note 4)				-500			mA	(Note 6)
	II	Input Current		3.6			10	mA	VI = 5.5V
			Control Pins	3.6			±1	mA	VI = 0V or VCC
			Data Pins	3.6			-5	mA	VI = 0V
							1	mA	VI = VCC
	IOFF	Power Off Leakage Current		0			±100	mA	0V £ VI or VO £ 5.5V
	IPU/PD	Power up/down 3-STATE		0–1.5V			±100	mA	VO = 0.5V to 3.0V
		Output Current							VI = GND or VCC
	IOZL	3-STATE Output Leakage Current		3.6			-5	mA	VO = 0.5V
	IOZH	3-STATE Output Leakage Current		3.6			5	mA	VO = 3.0V

74LVTH240 • 74LVT240

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