Fairchild Semiconductor 74F161ASJ, 74F161ASCX, 74F161ASC, 74F161APC, 74F163ASJX Datasheet
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April 1988
Revised July 1999
74F161A • 74F163A
Synchronous Presettable Binary Counter
General Description
The 74F161A and 74F163A are high-speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multi-stage counters. The 74F161A has an asynchronous MasterReset input that overrides all other inputs and forces the outputs LOW. The 74F163A has a Synchronous Reset input that overrides counting and parallel loading and allows the outputs to be simultaneously reset on the rising edge of the clock. The 74F161A and 74F163A are highspeed versions of the 74F161 and 74F163.
Features
■Synchronous counting and loading
■High-speed synchronous expansion
■Typical count frequency of 120 MHz
Ordering Code:
Order Number |
Package Number |
Package Description |
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74F161ASC |
M16A |
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow |
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74F161ASJ |
M16D |
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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74F161APC |
N16E |
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide |
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74F163ASC |
M16A |
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow |
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74F163ASJ |
M16D |
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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74F163APC |
N16E |
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
74F161A |
74F163A |
Counter Binary Presettable Synchronous 74F163A • 74F161A
© 1999 Fairchild Semiconductor Corporation |
DS009486 |
www.fairchildsemi.com |
74F161A • 74F163A
Logic Symbols
74F161A |
74F163A |
IEEE/IEC |
IEEE/IEC |
74F161A 74F163A
Unit Loading/Fan Out
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Pin Names |
Description |
U.L. |
Input IIH/IIL |
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HIGH/LOW |
Output IOH/IOL |
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CEP |
Count Enable Parallel Input |
1.0/1.0 |
20 μA/−0.6 mA |
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CET |
Count Enable Trickle Input |
1.0/2.0 |
20 μA/−1.2 mA |
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CP |
Clock Pulse Input (Active Rising Edge) |
1.0/1.0 |
20 μA/−0.6 mA |
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Asynchronous Master Reset Input (Active LOW) |
1.0/1.0 |
20 μA/−0.6 mA |
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MR |
(74F161A) |
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Synchronous Reset Input (Active LOW) |
1.0/2.0 |
20 μA/−1.2 mA |
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SR |
(74F163A) |
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P0–P3 |
Parallel Data Inputs |
1.0/1.0 |
20 μA/−0.6 mA |
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Parallel Enable Input (Active LOW) |
1.0/2.0 |
20 μA/−1.2 mA |
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PE |
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Q0–Q3 |
Flip-Flop Outputs |
50/33.3 |
−1 mA/20 mA |
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TC |
Terminal Count Output |
50/33.3 |
−1 mA/20 mA |
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www.fairchildsemi.com |
2 |
Functional Description
The 74F161A and 74F163A count in modulo-16 binary sequence. From state 15 (HHHH) they increment to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs (except due to Master Reset of the 74F161A) occur as a result of, and synchronous with, the LOW-to-HIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence: asynchronous reset (74F161A), synchronous reset (74F163A), parallel load, count-up and hold. Five control inputs—Master Reset (MR , 74F161A), Synchronous Reset (SR, 74F163A), Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET)—determine the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW. A LOW signal on SR overrides counting and parallel loading and allows all outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next
rising edge of CP. With PE and MR ('F161A) or SR (74F163A) HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting.
The 74F161A and 74F163A use D-type edge triggered flipflops and changing the SR, PE, CEP and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is HIGH and the counter is in state 15. To implement synchronous multi-stage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. Please refer to the 74F568 data sheet. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, counters or registers.
Logic Equations: Count Enable = CEP • CET • PE
TC = Q0 • Q1 • Q2 • Q3 • CET
Mode Select Table |
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State Diagram |
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CE |
Action on the Rising |
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SR |
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PE |
CET |
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(Note 1) |
P |
Clock Edge ( ) |
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L |
X |
X |
X |
Reset (Clear) |
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H |
L |
X |
X |
Load (Pn→Qn) |
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H |
H |
H |
H |
Count (Increment) |
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H |
H |
L |
X |
No Change (Hold) |
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H |
H |
X |
L |
No Change (Hold) |
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H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Note 1: For 74F163A only
Block Diagram
74F163A • 74F161A
3 |
www.fairchildsemi.com |
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