June 1991
Revised November 1999
74ACTQ16541
16-Bit Buffer/Line Driver with 3-STATE Outputs
General Description
The ACTQ16541 contains sixteen non-inverting buffers with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is byte controlled. Each byte has separate 3-STATE control inputs which can be shorted together for full 16-bit operation.
The ACTQ16541 utilizes Fairchild Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO output control for superior performance.
Features
■Utilizes Fairchild FACT Quiet Series technology
■Guaranteed simultaneous switching noise level and dynamic threshold performance
■Guaranteed pin-to-pin output skew
■Separate control logic for each byte
■16-bit version of the ACTQ541
■Outputs source/sink 24 mA
■Additional specs for Multiple Output Switching
■Output loading specs for both 50 pF and 250 pF loads
Ordering Code:
Order Number |
Package Number |
Package Description |
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74ACTQ16541SSC |
MS48A |
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide |
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74ACTQ16541MTD |
MTD48 |
48-Lead Thin Shrink Small Outline Package (TSSOP), MO-153, 6.1mm Wide |
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Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol |
Connection Diagram |
Pin Descriptions
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Pin Names |
Description |
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n |
Output Enable Input (Active LOW) |
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OE |
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I0–I15 |
Inputs |
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O0–O15 |
Outputs |
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FACT , Quiet Series , FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation
Outputs STATE-3 with Driver Buffer/Line Bit-16 74ACTQ16541
© 1999 Fairchild Semiconductor Corporation |
DS010936 |
www.fairchildsemi.com |
74ACTQ16541
Functional Description
The ACTQ16541 contains sixteen non-inverting buffers with 3-STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. The 3-STATE outputs are controlled by an Output Enable (OEn) input for each byte.
When OEn is LOW, the outputs are in 2-state mode. When
OEn is HIGH, the outputs are in the high impedance mode, but this does not interfere with entering new data into the inputs.
Logic Diagram
Truth Tables
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Inputs |
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Outputs |
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OE1 |
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OE2 |
I0–I7 |
O0–O7 |
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L |
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L |
H |
H |
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H |
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X |
X |
Z |
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X |
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H |
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Z |
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L |
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L |
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L |
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Inputs |
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Outputs |
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OE3 |
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OE4 |
I8–I15 |
O8–O15 |
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L |
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H |
H |
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H |
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X |
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Z |
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X |
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H |
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Z |
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L |
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H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 1) |
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Recommended Operating |
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Supply Voltage (VCC) |
− 0.5V to +7.0V |
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Conditions |
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DC Input Diode Current (IIK) |
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Supply Voltage (V |
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4.5V to 5.5V |
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VI = − 0.5V |
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− 20 mA |
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CC |
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Input Voltage (V ) |
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0V to V |
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I |
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CC |
VI = VCC + 0.5V |
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+20 mA |
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Output Voltage (V |
O |
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0V to V |
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CC |
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DC Output Diode Current (IOK) |
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Operating Temperature (T ) |
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− 40° C to +85° C |
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VO = − 0.5V |
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− 20 mA |
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A |
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Minimum Input Edge Rate (∆ V/∆ t) |
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125 mV/ns |
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VO = VCC + 0.5V |
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+20 mA |
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VIN from 0.8V to 2.0V |
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DC Output Voltage (VO) |
− 0.5V to VCC + 0.5V |
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VCC @ 4.5V, 5.5V |
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DC Output Source/Sink Current (IO) |
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± 50 mA |
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Note 1: Absolute maximum ratings are those values beyond which damage |
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DC VCC or Ground Current |
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to the device may occur. The databook specifications should be met, with- |
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out exception to ensure that the system design is reliable over its power |
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per Output Pin |
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± 50 mA |
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supply, temperature, and output/input loading variables. Fairchild does not |
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Storage Temperature |
− 65° C to +150° C |
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recommend operation of FACT circuits outside databook specifications. |
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DC Electrical Characteristics |
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Symbol |
Parameter |
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VCC |
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TA = +25° C |
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TA = − 40° C to +85° C |
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Units |
Conditions |
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(V) |
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Typ |
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Guaranteed Limits |
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VIH |
Minimum HIGH |
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4.5 |
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1.5 |
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2.0 |
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2.0 |
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V |
VOUT = 0.1V |
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Input Voltage |
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5.5 |
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1.5 |
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2.0 |
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2.0 |
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or VCC − |
0.1V |
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VIL |
Maximum LOW |
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4.5 |
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1.5 |
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0.8 |
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0.8 |
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V |
VOUT = 0.1V |
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Input Voltage |
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5.5 |
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1.5 |
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0.8 |
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0.8 |
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or VCC − |
0.1V |
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VOH |
Minimum HIGH |
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4.5 |
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4.49 |
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4.4 |
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4.4 |
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V |
IOUT = − |
50 µ A |
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Output Voltage |
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5.5 |
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5.49 |
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5.4 |
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5.4 |
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VIN = VIL or VIH |
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4.5 |
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3.86 |
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3.76 |
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V |
IOH = − 24 mA |
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5.5 |
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4.86 |
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4.76 |
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IOH = − 24 mA (Note 2) |
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VOL |
Maximum LOW |
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4.5 |
0.001 |
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0.1 |
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0.1 |
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V |
IOUT = 50 µ A |
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Output Voltage |
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5.5 |
0.001 |
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0.1 |
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0.1 |
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VIN = VIL or VIH |
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4.5 |
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0.36 |
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0.44 |
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V |
IOL = 24 mA |
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5.5 |
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0.36 |
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0.44 |
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IOL = 24 mA (Note 2) |
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IOZ |
Maximum 3-STATE |
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5.5 |
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± |
0.5 |
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± |
5.0 |
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µ A |
VI = VIL, VIH |
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Leakage Current |
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VO = VCC, GND |
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IIN |
Maximum Input Leakage Current |
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5.5 |
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± |
0.1 |
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1.0 |
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µ A |
VI = VCC, GND |
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ICCT |
Maximum ICC/Input |
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5.5 |
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0.6 |
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1.5 |
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mA |
VI = VCC − 2.1V |
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ICC |
Max Quiescent Supply Current |
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5.5 |
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8.0 |
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80.0 |
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µ A |
VIN = VCC or GND |
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IOLD |
Minimum Dynamic |
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5.5 |
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75 |
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mA |
VOLD = 1.65V Max |
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IOHD |
Output Current (Note 3) |
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− 75 |
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mA |
VOHD = 3.85V Min |
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VOLP |
Quiet Output |
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5.0 |
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0.5 |
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0.8 |
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V |
Figure 1, Figure 2 |
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Maximum Dynamic VOL |
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(Note 5)(Note 6) |
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VOLV |
Quiet Output |
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5.0 |
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− |
0.5 |
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1.0 |
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V |
Figure 1, Figure 2 |
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Minimum Dynamic VOL |
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(Note 5)(Note 6) |
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VOHP |
Maximum |
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5.0 |
V |
OH |
+ |
V |
OH |
+ |
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V |
Figure 1, Figure 2 |
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Overshoot |
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(Note 4)(Note 6) |
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1.0 |
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1.5 |
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VOHV |
Minimum |
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5.0 |
VOH − 1.0 |
VOH − |
1.8 |
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V |
Figure 1, Figure 2 |
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VCC Droop |
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(Note 4)(Note 6) |
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VIHD |
Minimum HIGH Dynamic Input Voltage Level |
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5.0 |
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1.7 |
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2.0 |
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V |
(Note 4)(Note 7) |
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VILD |
Maximum LOW Dynamic Input Voltage Level |
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5.0 |
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1.2 |
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0.8 |
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V |
(Note 4)(Note 7) |
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Note 2: All outputs loaded; thresholds associated with output under test.
Note 3: Maximum test duration 2.0 ms; one output loaded at a time.
Note 4: Worst case package.
Note 5: Maximum number of outputs that can switch simultaneously is n. (n − 1) outputs are switched LOW and one output held LOW.
Note 6: Maximum number of outputs that can switch simultaneously is n. (n − 1) outputs are switched HIGH and one output held HIGH.
Note 7: Maximum number of data inputs (n) switching. (n − 1) input switching 0V to 3V. Input under test switching 3V to threshold (VILD).
74ACTQ16541
3 |
www.fairchildsemi.com |
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