Fairchild Semiconductor 74ACTQ574SJX, 74ACTQ574SJ, 74ACTQ574SCX, 74ACTQ574SC, 74ACTQ574PC Datasheet
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January 1990
Revised November 1999
74ACQ574 • 74ACTQ574
Quiet Series Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
The ACQ/ACTQ574 is a high-speed, low-power octal D- type flip-flop with a buffered Common Clock (CP) and a buffered common Output Enable (OE). The information presented to the D inputs is stored in the flip-flops on the LOW-to-HIGH clock (CP) transition.
ACQ/ACTQ574 utilizes FACT Quiet Series technology to guarantee quiet output switching and improve dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector in addition to a split ground bus for superior performance.
The ACQ/ACTQ574 is functionally identical to the ACTQ374 but with different pin-out.
Features
■ICC and IOZ reduced by 50%
■Guaranteed simultaneous switching noise level and dynamic threshold performance
■Guaranteed pin-to-pin skew AC performance
■Inputs and outputs on opposite sides of the package allowing easy interface with microprocessors
■Functionally identical to the ACQ/ACTQ374
■3-STATE outputs drive bus lines or buffer memory address registers
■Outputs source/sink 24 mA
■Faster prop delays than the standard AC/ACT574
Ordering Code:
Order Number |
Package Number |
Package Description |
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74ACQ574SC |
M20B |
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body |
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74ACQ574SJ |
M20D |
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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74ACQ574PC |
N20A |
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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74ACTQ574SC |
M20B |
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body |
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74ACTQ574SJ |
M20D |
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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74ACTQ574PC |
N20A |
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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Device also available in Tape and Reel. Specify by appending suffix “X” to the ordering code.
Connection Diagram |
Pin Descriptions |
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Pin Names |
Description |
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D0–D7 |
Data Inputs |
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CP |
Clock Pulse Input |
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3-STATE Output Enable Input |
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OE |
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O0–O7 |
3-STATE Outputs |
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FACT , Quiet Series , FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.
Outputs STATE-3 with Flop-Flip Type-D Octal Series Quiet 74ACTQ574 • 74ACQ574
© 1999 Fairchild Semiconductor Corporation |
DS010634 |
www.fairchildsemi.com |
74ACQ574 • 74ACTQ574
Logic Symbols
IEEE/IEC
Logic Diagram
Functional Description
The ACQ/ACTQ574 consists of eight edge-triggered flipflops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops.
Function Table
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Inputs |
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Internal |
Outputs |
Function |
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OE |
CP |
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D |
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Q |
ON |
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H |
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H |
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L |
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NC |
Z |
Hold |
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H |
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H |
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H |
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NC |
Z |
Hold |
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H |
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L |
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L |
Z |
Load |
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H |
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H |
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H |
Z |
Load |
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L |
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L |
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L |
L |
Data Available |
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L |
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H |
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H |
H |
Data Available |
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L |
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H |
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L |
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NC |
NC |
No Change in Data |
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L |
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H |
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H |
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NC |
NC |
No Change in Data |
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H = HIGH Voltage Level |
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L = LOW Voltage Level |
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X = Immaterial |
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Z = High Impedance |
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= |
LOW-to-HIGH Transition |
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NC = |
No Change |
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Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) |
− 0.5V to + 7.0V |
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DC Input Diode Current (IIK) |
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VI = |
− 0.5V |
− 20 mA |
VI = |
VCC + 0.5V |
+ 20 mA |
DC Input Voltage (VI) |
− 0.5V to VCC + 0.5V |
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DC Output Diode Current (IOK) |
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VO = |
− 0.5V |
− 20 mA |
VO = |
VCC + 0.5V |
+ 20 mA |
DC Output Voltage (VO) |
− 0.5V to VCC + 0.5V |
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DC Output Source |
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or Sink Current (IO) |
± 50 mA |
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DC VCC or Ground Current |
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per Output Pin (ICC or IGND) |
± 50 mA |
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Storage Temperature (TSTG) |
− 65° C to + 150° C |
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DC Latch-Up Source or |
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Sink Current |
± 300 mA |
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Junction Temperature (TJ) |
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PDIP |
140° C |
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Recommended Operating
Conditions
Supply Voltage (VCC) |
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ACQ |
2.0V to 6.0V |
ACTQ |
4.5V to 5.5V |
Input Voltage (VI) |
0V to VCC |
Output Voltage (VO) |
0V to VCC |
Operating Temperature (TA) |
− 40° C to + 85° C |
Minimum Input Edge Rate ∆ V/∆ t |
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ACQ Devices |
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VIN from 30% to 70% of VCC |
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VCC @ 3.0V, 4.5V, 5.5V |
125 mV/ns |
Minimum Input Edge Rate ∆ V/∆ t |
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ACTQ Devices |
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VIN from 0.8V to 2.0V |
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VCC @ 4.5V, 5.5V |
125 mV/ns |
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for ACQ
Symbol |
Parameter |
VCC |
TA = + 25° C |
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TA = − 40° C to + 85° C |
Units |
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Conditions |
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(V) |
Typ |
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Guaranteed Limits |
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VIH |
Minimum HIGH Level |
3.0 |
1.5 |
2.1 |
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2.1 |
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VOUT = |
0.1V |
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Input Voltage |
4.5 |
2.25 |
3.15 |
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3.15 |
V |
or VCC − |
0.1V |
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5.5 |
2.75 |
3.85 |
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3.85 |
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VIL |
Maximum LOW Level |
3.0 |
1.5 |
0.9 |
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0.9 |
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VOUT = |
0.1V |
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Input Voltage |
4.5 |
2.25 |
1.35 |
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1.35 |
V |
or VCC − |
0.1V |
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5.5 |
2.75 |
1.65 |
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1.65 |
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VOH |
Minimum HIGH Level |
3.0 |
2.99 |
2.9 |
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2.9 |
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Output Voltage |
4.5 |
4.49 |
4.4 |
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4.4 |
V |
IOUT = |
− |
50 µ A |
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5.5 |
5.49 |
5.4 |
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5.4 |
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VIN = |
VIL or VIH |
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3.0 |
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2.56 |
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2.46 |
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IOH = |
− |
12 mA |
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4.5 |
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3.86 |
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3.76 |
V |
IOH = |
− |
24 mA |
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5.5 |
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4.86 |
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4.76 |
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IOH = |
− 24 mA (Note 2) |
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VOL |
Maximum LOW Level |
3.0 |
0.002 |
0.1 |
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0.1 |
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Output Voltage |
4.5 |
0.001 |
0.1 |
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0.1 |
V |
IOUT = |
50 µ A |
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5.5 |
0.001 |
0.1 |
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0.1 |
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VIN = |
VIL or VIH |
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3.0 |
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0.36 |
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0.44 |
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IOL = |
12 mA |
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4.5 |
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0.36 |
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0.44 |
V |
IOL = |
24 mA |
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5.5 |
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0.36 |
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0.44 |
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IOL = |
24 mA (Note 2) |
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IIN |
Maximum Input |
5.5 |
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± 0.1 |
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± 1.0 |
µ A |
VI = |
VCC, GND |
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(Note 4) |
Leakage Current |
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IOLD |
Minimum Dynamic |
5.5 |
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75 |
mA |
VOLD = |
1.65V Max |
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IOHD |
Output Current (Note 3) |
5.5 |
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− 75 |
mA |
VOHD = |
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3.85V Min |
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ICC |
Maximum Quiescent |
5.5 |
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4.0 |
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40.0 |
µ A |
VIN = |
VCC |
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(Note 4) |
Supply Current |
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or GND |
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IOZ |
Maximum 3-STATE |
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VI (OE) = VIL, VIH |
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Leakage Current |
5.5 |
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± 0.25 |
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± 2.5 |
µ A |
VI = |
VCC, GND |
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VO = |
VCC, GND |
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74ACTQ574 • 74ACQ574
3 |
www.fairchildsemi.com |
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