Fairchild Semiconductor 74ACTQ373SC, 74ACTQ373QSCX, 74ACTQ373QSC, 74ACTQ373PC, 74ACTQ373CW Datasheet
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July 1989
Revised November 1999
74ACQ373 • 74ACTQ373
Quiet Series Octal Transparent Latch with 3-STATE Outputs
General Description
The ACQ/ACTQ373 consists of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the HIGH impedance state.
The ACQ/ACTQ373 utilizes Fairchild Quiet Series technology to guarantee quiet output switching and improve dynamic threshold performance. features GTO output control and undershoot corrector in addition to a split ground bus for superior performance.
Features
■ICC and IOZ reduced by 50%
■Guaranteed simultaneous switching noise level and dynamic threshold performance
■Guaranteed pin-to-pin skew AC performance
■Improved latch up immunity
■Eight latches in a single package
■3-STATE outputs drive bus lines or buffer memory address registers
■Outputs source/sink 24 mA
■Faster prop delays than the standard AC/ACT373
Ordering Code:
Order Number |
Package Number |
Package Description |
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74ACQ373SC |
M20B |
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body |
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74ACQ373SJ |
M20D |
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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74ACQ373PC |
N20A |
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001m 0.300” Wide |
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74ACTQ373SC |
M20B |
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body |
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74ACTQ373SJ |
M20D |
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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74ACQT373QSC |
MQA20 |
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide |
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74ACTQ373PC |
N20A |
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001m 0.300” Wide |
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Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram |
Pin Descriptions |
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Pin Names |
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Description |
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D0–D7 |
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Data Inputs |
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LE |
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Latch Enable Input |
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Output Enable Input |
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OE |
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O0–O7 |
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3-STATE Latch Outputs |
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FACT |
, Quiet Series |
, FACT Quiet Series |
, and GTO are trademarks of Fairchild Semiconductor Corporation. |
Outputs STATE-3 with Latch Transparent Octal Series Quiet 74ACTQ373 • 74ACQ373
© 1999 Fairchild Semiconductor Corporation |
DS010237 |
www.fairchildsemi.com |
74ACQ373 • 74ACTQ373
Logic Symbols
IEEE/IEC
Logic Diagram
Functional Description
The ACQ/ACTQ373 contains eight D-type latches with 3- STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs at setup time preceding the HIGH- to-LOW transition of LE. The 3-STATE standard outputs are controlled by the Output Enable (OE) input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.
Truth Table
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Inputs |
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Outputs |
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LE |
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OE |
Dn |
On |
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X |
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H |
X |
Z |
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H |
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L |
L |
L |
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H |
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L |
H |
H |
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L |
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L |
X |
O0 |
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H = |
HIGH Voltage Level |
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L = |
LOW Voltage Level |
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Z = |
High Impedance |
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X = |
Immaterial |
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O0 = |
Previous O0 before HIGH-to-LOW transition of Latch Enable |
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Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) |
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− 0.5V to + 7.0V |
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DC Input Diode Current (IIK) |
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VI = |
− 0.5V |
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− 20 mA |
VI = |
VCC + 0.5V |
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+ 20 mA |
DC Input Voltage (VI) |
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− 0.5V to VCC + 0.5V |
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DC Output Diode Current (IOK) |
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VO = |
− 0.5V |
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− 20 mA |
VO = |
VCC + 0.5V |
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+ 20 mA |
DC Output Voltage (VO) |
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− 0.5V to VCC + 0.5V |
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DC Output Source |
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or Sink Current (IO) |
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± 50 mA |
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DC VCC or Ground Current |
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per Output Pin (I |
or I |
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± 50 mA |
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CC |
GND |
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Storage Temperature (TSTG) |
− 65° C to + 150° C |
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DC Latchup Source |
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or Sink Current |
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± 300 mA |
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Junction Temperature (TJ) |
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PDIP |
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140° C |
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Recommended Operating
Conditions
Supply Voltage (VCC) |
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ACQ |
2.0V to 6.0V |
ACTQ |
4.5V to 5.5V |
Input Voltage (V ) |
0V to V |
I |
CC |
Output Voltage (VO) |
0V to VCC |
Operating Temperature (TA) |
− 40° C to + 85° C |
Minimum Input Edge Rate ∆ V/∆ t |
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ACQ Devices |
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VIN from 30% to 70% of VCC |
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VCC @ 3.0V, 4.5V, 5.5V |
125 mV/ns |
Minimum Input Edge Rate ∆ V/∆ t |
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ACTQ Devices |
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VCC @ 4.5V, 5.5V |
125 mV/ns |
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for ACQ
Symbol |
Parameter |
VCC |
TA = + 25° C |
TA = − 40° C to + 85° C |
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Conditions |
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(V) |
Typ |
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Guaranteed Limits |
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VIH |
Minimum HIGH Level |
3.0 |
1.5 |
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2.1 |
2.1 |
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VOUT = |
0.1V |
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Input Voltage |
4.5 |
2.25 |
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3.15 |
3.15 |
V |
or VCC − |
0.1V |
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5.5 |
2.75 |
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3.85 |
3.85 |
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VIL |
Maximum LOW Level |
3.0 |
1.5 |
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0.9 |
0.9 |
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VOUT = |
0.1V |
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Input Voltage |
4.5 |
2.25 |
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1.35 |
1.35 |
V |
or VCC − |
0.1V |
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5.5 |
2.75 |
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1.65 |
1.65 |
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VOH |
Minimum HIGH Level |
3.0 |
2.99 |
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2.9 |
2.9 |
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Output Voltage |
4.5 |
4.49 |
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4.4 |
4.4 |
V |
IOUT = |
− |
50 µ A |
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5.5 |
5.49 |
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5.4 |
5.4 |
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VIN = |
VIL or VIH |
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3.0 |
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2.56 |
2.46 |
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IOH = |
− |
12 mA |
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4.5 |
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3.86 |
3.76 |
V |
IOH = |
− |
24 mA |
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5.5 |
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4.86 |
4.76 |
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IOH = |
− 24 mA (Note 2) |
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VOL |
Maximum LOW Level |
3.0 |
0.002 |
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0.1 |
0.1 |
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Output Voltage |
4.5 |
0.001 |
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0.1 |
0.1 |
V |
IOUT = |
50 µ A |
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5.5 |
0.001 |
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0.1 |
0.1 |
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VIN = |
VIL or VIH |
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3.0 |
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0.36 |
0.44 |
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IOL = |
12 mA |
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4.5 |
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0.36 |
0.44 |
V |
IOL = |
24 mA |
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5.5 |
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0.36 |
0.44 |
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IOL = |
24 mA (Note 2) |
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IIN (Note 4) |
Maximum Input Leakage Current |
5.5 |
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± |
0.1 |
± 1.0 |
µ A |
VI = |
VCC, GND |
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IOLD |
Minimum Dynamic |
5.5 |
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75 |
mA |
VOLD = |
1.65V Max |
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IOHD |
Output Current (Note 3) |
5.5 |
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− 75 |
mA |
VOHD = |
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3.85V Min |
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ICC (Note 4) |
Maximum Quiescent Supply Current |
5.5 |
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4.0 |
40.0 |
µ A |
VIN = |
VCC or GND |
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IOZ |
Maximum 3-STATE |
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VI (OE) = VIL, VIH |
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Leakage Current |
5.5 |
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± |
0.25 |
± 2.5 |
µ A |
VI = |
VCC, GND |
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VO = |
VCC, GND |
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VOLP |
Quiet Output |
5.0 |
1.1 |
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1.5 |
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V |
Figure 1, Figure 2 |
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Maximum Dynamic VOL |
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(Note 5)(Note 6) |
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VOLV |
Quiet Output |
5.0 |
− 0.6 |
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− 1.2 |
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V |
Figure 2, Figure 2 |
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Maximum Dynamic VOL |
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(Note 5)(Note 6) |
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74ACTQ373 • 74ACQ373
3 |
www.fairchildsemi.com |
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