Fairchild Semiconductor 74ACTQ544SPC, 74ACTQ544SCX, 74ACTQ544SC, 74ACTQ544CW Datasheet

0 (0)

March 1990

Revised September 2000

74ACQ544 • 74ACTQ544

Quiet Series Octal Registered Transceiver with 3-STATE Outputs

General Description

The ACQ/ACTQ544 is an inverting octal transceiver containing two sets of D-type registers for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent input and output control in either direction of data flow. The 544 inverts data in both directions.

The ACQ/ACTQ utilizes Fairchild FACT Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector in addition to a split ground bus for superior performance.

Features

Guaranteed simultaneous switching noise level and dynamic threshold performance

Guaranteed pin-to-pin skew AC performance

8-bit inverting octal latched transceiver

Separate controls for data flow in each direction

Back-to-back registers for storage

Outputs source/sink 24 mA

Ordering Code:

Order Number

Package Number

Package Description

 

 

 

74ACQ544SC

M24B

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

 

 

 

74ACQ544SPC

N24C

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

 

 

 

74ACTQ544SC

M24B

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

 

 

 

74ACTQ544SPC

N24C

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

 

 

 

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

 

 

 

 

 

 

 

 

Pin Names

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A-to-B Output Enable Input (Active LOW)

 

 

 

OEAB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B-to-A Output Enable Input (Active LOW)

 

 

 

OEBA

 

 

 

 

 

 

 

 

 

 

 

 

 

A-to-B Enable Input (Active LOW)

 

 

 

CEAB

 

 

 

 

 

 

 

 

 

 

 

 

 

B-to-A Enable Input (Active LOW)

 

 

 

CEBA

 

 

 

 

 

 

 

 

 

 

 

 

A-to-B Latch Enable Input (Active LOW)

 

 

 

LEAB

 

 

 

 

 

 

 

 

 

 

 

 

 

B-to-A Latch Enable Input (Active LOW)

 

 

 

LEBA

 

 

 

 

 

 

 

 

 

 

 

 

 

A-to-B Data Inputs or

 

 

 

A

 

 

–A

 

 

 

 

 

0

7

 

 

 

 

 

 

 

 

 

 

 

 

 

B-to-A 3-STATE Outputs

 

 

 

 

 

 

 

B-to-A Data Inputs or

 

 

 

B

 

–B

 

 

 

 

 

0

7

 

 

 

 

 

 

 

 

 

 

 

 

 

A-to-B 3-STATE Outputs

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FACT , Quiet Series , FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.

Outputs STATE-3 with Transceiver Registered Octal Series Quiet 74ACTQ544 • 74ACQ544

© 2000 Fairchild Semiconductor Corporation

DS010685

www.fairchildsemi.com

Fairchild Semiconductor 74ACTQ544SPC, 74ACTQ544SCX, 74ACTQ544SC, 74ACTQ544CW Datasheet

74ACQ544 • 74ACTQ544

Logic Symbols

IEEE/IEC

Logic Diagram

Functional Description

The ACQ/ACTQ544 contains two sets of eight D-type latches, with separate input and output controls for each set. For data flow from A to B, for example, the A-to-B Enable (CEAB) input must be LOW in order to enter data from A0 –A7 or take data from B0 –B7, as indicated in the

Data I/O Control Table. With CEAB LOW, a LOW signal on the A-to-B Latch Enable (LEAB) input makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both LOW, the 3-STATE B output buffers are active and reflect the data present at the output of the A latches. Control of data flow from B to A is similar, but using the CEBA, LEBA and OEBA inputs.

Data I/O Control Table

 

 

Inputs

 

 

 

Latch

Output

 

 

 

 

 

 

 

 

 

CEAB

LEAB

OEAB

 

Status

Buffers

 

 

 

 

 

 

 

 

 

 

H

 

X

 

X

 

Latched

High Z

 

X

 

H

 

X

 

Latched

 

L

 

L

 

X

 

Transparent

 

X

 

X

 

H

 

High Z

 

L

 

X

 

L

 

Driving

H = HIGH Voltage Level

L = LOW Voltage Level X = Immaterial

A-to-B data flow shown; B-to-A flow control is the same, except using CEBA, LEBA and OEBA

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

www.fairchildsemi.com

2

Absolute Maximum Ratings(Note 1)

Supply Voltage (VCC)

− 0.5V to + 7.0V

DC Input Diode Current (IIK)

 

VI =

− 0.5V

− 20 mA

VI =

VCC + 0.5V

+ 20 mA

DC Input Voltage (VI)

− 0.5V to VCC + 0.5V

DC Output Diode Current (IOK)

 

VO =

− 0.5V

− 20 mA

VO =

VCC + 0.5V

+ 20 mA

DC Output Voltage (VO)

− 0.5V to VCC + 0.5V

DC Output Source

 

or Sink Current (IO)

± 50 mA

DC VCC or Ground Current

 

per Output Pin (ICC or IGND)

± 50 mA

Storage Temperature (TSTG)

− 65° C to + 150° C

DC Latch-up Source or

 

Sink Current

± 300 mA

Junction Temperature (TJ)

 

PDIP

140° C

Recommended Operating

Conditions

Supply Voltage VCC

 

ACQ

2.0V to 6.0V

ACTQ

4.5V to 5.5V

Input Voltage (VI)

0V to VCC

Output Voltage (VO)

0V to VCC

Operating Temperature (TA)

− 40° C to + 85° C

Minimum Input Edge Rate ∆ V/∆ t

 

ACQ Devices

 

VIN from 30% to 70% of VCC

 

VCC @3.0V, 4.5V, 5.5V

125 mV/ns

Minimum Input Edge Rate ∆ V/∆ t

 

ACTQ Devices

 

VIN from 0.8V to 2.0V

 

VCC @ 4.5V, 5.5V

125 mV/ns

Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.

DC Electrical Characteristics for ACQ

Symbol

Parameter

VCC

TA = + 25° C

TA = − 40° C to + 85° C

Units

 

Conditions

 

 

(V)

Typ

Guaranteed Limits

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VIH

Minimum HIGH Level

3.0

1.5

2.1

2.1

 

VOUT =

0.1V

 

Input Voltage

4.5

2.25

3.15

3.15

V

or VCC

0.1V

 

 

5.5

2.75

3.85

3.85

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VIL

Maximum LOW Level

3.0

1.5

0.9

0.9

 

VOUT =

0.1V

 

Input Voltage

4.5

2.25

1.35

1.35

V

or VCC

0.1V

 

 

5.5

2.75

1.65

1.65

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VOH

Minimum HIGH Level

3.0

2.99

2.9

2.9

 

 

 

 

 

 

Output Voltage

4.5

4.49

4.4

4.4

V

IOUT =

50 µ A

 

 

5.5

5.49

5.4

5.4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VIN =

VIL or VIH

 

 

3.0

 

2.56

2.46

 

IOH =

12 mA

 

 

4.5

 

3.86

3.76

V

IOH =

24 mA

 

 

5.5

 

4.86

4.76

 

IOH =

24 mA (Note 2)

VOL

Maximum LOW Level

3.0

0.002

0.1

0.1

 

 

 

 

 

 

Output Voltage

4.5

0.001

0.1

0.1

V

IOUT =

50 µ A

 

 

5.5

0.001

0.1

0.1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VIN =

VIL or VIH

 

 

3.0

 

0.36

0.44

 

IOL =

12 mA

 

 

4.5

 

0.36

0.44

V

IOL =

24 mA

 

 

5.5

 

0.36

0.44

 

IOL =

24 mA (Note 2)

IIN

Maximum Input

5.5

 

± 0.1

± 1.0

µ A

VI =

VCC, GND

(Note 4)

Leakage Current

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IOLD

Minimum Dynamic

5.5

 

 

75

mA

VOLD =

1.65V Max

IOHD

Output Current (Note 3)

5.5

 

 

− 75

mA

VOHD =

3.85V Min

ICC (Note 4)

Maximum Quiescent Supply Current

5.5

 

8.0

80.0

µ A

VIN=

VCC or GND

IOZT

Maximum I/O

 

 

 

 

 

VI (OE) =

VIL, VIH

 

Leakage Current

5.5

 

± 0.6

± 6.0

µ A

VI =

VCC, GND

 

 

 

 

 

 

 

VO =

VCC, GND

VOLP

Quiet Output

5.0

1.1

1.5

 

V

Figures 1, 2

 

Maximum Dynamic VOL

 

(Note 5)(Note 6)

 

 

 

 

 

 

74ACTQ544 • 74ACQ544

3

www.fairchildsemi.com

Loading...
+ 6 hidden pages