May 1991
Revised December 1998
74ACTQ823
Quiet Seriesä 9-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description
The ACTQ823 is a 9-bit buffered register. It features Clock Enable and Clear which are ideal for parity bus interfacing in high performance microprogramming systems. The ACTQ823 utilizes Fairchild Quiet Seriesä technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Seriesä features GTOä output control and undershoot corrector in addition to a split ground bus for superior performance.
Features
■Guaranteed simultaneous switching noise level and dynamic threshold performance
■Guaranteed pin-to-pin skew AC performance
■Inputs and outputs on opposite sides of package allow easy interface with microprocessors
■Improved latch-up immunity
■Has TTL-compatible inputs
Ordering Code:
Order Number |
Package Number |
Package Description |
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74ACTQ823SC |
M24B |
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body |
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74ACTQ823SPC |
N24C |
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide |
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Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering form.
Logic Symbols |
Connection Diagram |
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Pin Assignment |
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for DIP and SOIC |
IEEE/IEC
Pin Descriptions
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Pin Names |
Description |
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D0–D8 |
Data Inputs |
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O0–O8 |
Data Outputs |
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Output Enable |
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OE |
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Clear |
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CLR |
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CP |
Clock Input |
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Clock Enable |
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EN |
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FACTä, Quiet Seriesä, FACT Quiet Seriesä and GTOä are trademarks of Fairchild Semiconductor Corporation.
Outputs STATE-3 with Flop-Flip Type-D Bit-9 äSeries Quiet 74ACTQ823
© 1999 Fairchild Semiconductor Corporation |
DS010921.prf |
www.fairchildsemi.com |
74ACTQ823
Functional Description
The ACTQ823 consists of nine D-type edge-triggered flipflops. These have 3-STATE outputs for bus systems organized with inputs and outputs on opposite sides. The buffered clock (CP) and buffered Output Enable (OE) are common to all flip-flops. The flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH CP transition. With OE LOW, the contents of the flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. In addition to the Clock and Output
Enable pins, there are Clear (CLR) and Clock Enable (EN) pins. These devices are ideal for parity bus interfacing in high performance systems.
When CLR is LOW and OE is LOW, the outputs are LOW. When CLR is HIGH, data can be entered into the flip-flops. When EN is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When the EN is HIGH, the outputs do not change state, regardless of the data or clock input transitions.
Function Table
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Inputs |
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Internal |
Output |
Function |
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CP |
D |
Q |
O |
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OE |
CLR |
EN |
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H |
X |
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L |
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L |
L |
Z |
High Z |
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H |
X |
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L |
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H |
H |
Z |
High Z |
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H |
L |
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X |
X |
X |
L |
Z |
Clear |
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L |
L |
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X |
X |
X |
L |
L |
Clear |
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H |
H |
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H |
X |
X |
NC |
Z |
Hold |
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L |
H |
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H |
X |
X |
NC |
NC |
Hold |
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H |
H |
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L |
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L |
L |
Z |
Load |
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H |
H |
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L |
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H |
H |
Z |
Load |
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L |
H |
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L |
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L |
L |
L |
Load |
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L |
H |
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L |
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H |
H |
H |
Load |
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H = HIGH Voltage Level |
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Z = High Impedance |
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L = LOW Voltage Level |
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= LOW-to-HIGH Transition |
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X = Immaterial |
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NC = No Change |
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Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) |
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−0.5V to +7.0V |
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DC Input Diode Current (IIK) |
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VI = −0.5V |
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−20 mA |
VI = VCC + 0.5V |
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+20 mA |
DC Input Voltage (VI) |
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−0.5V to VCC + 0.5V |
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DC Output Diode Current (IOK) |
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VO = −0.5V |
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−20 mA |
VO = VCC + 0.5V |
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+20 mA |
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DC Output Voltage (VO) |
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−0.5V to VCC + 0.5V |
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DC Output Source |
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or Sink Current (IO) |
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± 50 mA |
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DC VCC or Ground Current |
± 50 mA |
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per Output Pin (I |
CC |
or I |
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GND |
−65°C to +150°C |
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Storage Temperature (TSTG) |
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DC Latch-Up Source |
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or Sink Current |
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± 300 mA |
Junction Temperature (TJ) |
140°C |
PDIP |
Recommended Operating
Conditions
Supply Voltage (VCC) |
4.5V to 5.5V |
Input Voltage (VI) |
0V to VCC |
Output Voltage (VO) |
0V to VCC |
Operating Temperature (TA) |
−40°C to +85°C |
Minimum Input Edge Rate V/ t |
125 mV/ns |
VIN from 0.8V to 2.0V |
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VCC @ 4.5V, 5.5V |
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Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACTä circuits outside databook specifications.
DC Electrical Characteristics for ACTQ
Symbol |
Parameter |
VCC |
TA = +25°C |
TA = −40°C to +85°C |
Units |
Conditions |
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(V) |
Typ |
Guaranteed Limits |
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VIH |
Minimum HIGH Level Input Voltage |
4.5 |
1.5 |
2.0 |
2.0 |
V |
VOUT = 0.1V |
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5.5 |
1.5 |
2.0 |
2.0 |
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or VCC − 0.1V |
VIL |
Maximum LOW Level |
4.5 |
1.5 |
0.8 |
0.8 |
V |
VOUT = 0.1V |
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Input Voltage |
5.5 |
1.5 |
0.8 |
0.8 |
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or VCC − 0.1V |
VOH |
Minimum HIGH Level |
4.5 |
4.49 |
4.4 |
4.4 |
V |
IOUT = −50 μA |
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Output Voltage |
5.5 |
5.49 |
5.4 |
5.4 |
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VIN = VILor VIH |
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4.5 |
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3.86 |
3.76 |
V |
IOH = −24 mA |
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5.5 |
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4.86 |
4.76 |
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IOH = −24 mA (Note 2) |
VOL |
Maximum LOW Level |
4.5 |
0.001 |
0.1 |
0.1 |
V |
IOUT = 50 μA |
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Output Voltage |
5.5 |
0.001 |
0.1 |
0.1 |
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VIN = VILor VIH |
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4.5 |
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0.36 |
0.44 |
V |
IOL = 24 mA |
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5.5 |
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0.36 |
0.44 |
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IOL = 24 mA (Note 2) |
IIN |
Maximum Input Leakage Current |
5.5 |
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± 0.1 |
± 1.0 |
μA |
VI = VCC, GND |
IOZ |
Maximum 3-STATE |
5.5 |
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± 0.5 |
± 5.0 |
μA |
VI = VIL, VIH |
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Leakage Current |
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VO = VCC, GND |
CCT |
Maximum ICC/Input |
5.5 |
0.6 |
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1.5 |
mA |
VI = VCC − 2.1V |
OLD |
Minimum Dynamic |
5.5 |
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75 |
mA |
VOLD = 1.65V Max |
IOHD |
Output Current (Note 2) |
5.5 |
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−75 |
mA |
VOHD = 3.85V Min |
ICC |
Maximum Quiescent Supply Current |
5.5 |
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8.0 |
80.0 |
μA |
VIN = VCC or GND |
VOLP |
Quiet Output |
5.0 |
1.1 |
1.5 |
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V |
Figure 1, Figure 2 |
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Maximum Dynamic VOL |
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(Note 5)(Note 6) |
VOLV |
Quiet Output |
5.0 |
−0.6 |
−1.2 |
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V |
Figure 1, Figure 2 |
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Minimum Dynamic VOL |
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(Note 5)(Note 6) |
VIHD |
Minimum HIGH Level Dynamic Input Voltage |
5.0 |
1.9 |
2.2 |
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V |
(Note 5)(Note 7) |
VILD |
Maximum LOW Level Dynamic Input Voltage |
5.0 |
1.2 |
0.8 |
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V |
(Note 5)(Note 7) |
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: PDIP package.
Note 6: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND.
74ACTQ823
3 |
www.fairchildsemi.com |
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