Fairchild Semiconductor 74ACTQ16543SSCX, 74ACTQ16543SSC, 74ACTQ16543MTDX, 74ACTQ16543MTD, 74ACTQ16543CW Datasheet
December 1991
Revised December 1998
74ACTQ16543
16-Bit Registered Transceiver with 3-STATE Outputs
General Description
The ACTQ16543 contains sixteen non-inverting transceivers containing two sets of D-type registers for temporary storage of data flowing in either direction. Each byte has separate control inputs which can be shorted together for full 16-bit operation. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent input and output control in either direction of data flow.
The ACTQ16543 utilizes Fairchild Quiet Seriesä technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Seriesä features GTOä output control and undershoot corrector for superior performance.
Features
■Utilizes Fairchild FACT Quiet Series technology
■Guaranteed simultaneous switching noise level and dynamic threshold performance
■Guaranteed pin-to-pin output skew
■Independent registers for A and B buses
■Separate controls for data flow in each direction
■Back-to-back registers for storage
Multiplexed real-time and stored data transfers
■Separate control logic for each byte
■16-bit version of the ACTQ543
■Outputs source/sink 24 mA
■Additional specs for Multiple Output Switching
■Output loading specs for both 50 pF and 250pF loads
Ordering Code:
Order Number |
Package Number |
Package Description |
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74ACTQ16543SSC |
MS56A |
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide |
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74ACTQ16543MTD |
MTD56 |
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide |
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Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol |
Pin Descriptions |
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Pin Names |
Descriptions |
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n |
A-to-B Output Enable Input (Active LOW) |
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OEAB |
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n |
B-to-A Output Enable Input (Active LOW) |
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OEBA |
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A-to-B Enable Input (Active LOW) |
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CEAB |
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B-to-A Enable Input (Active LOW) |
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CEBA |
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n |
A-to-B Latch Enable Input (Active LOW) |
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LEAB |
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n |
B-to-A Latch Enable Input (Active LOW) |
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LEBA |
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A0–A15 |
A-to-B Data Inputs or |
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B-to-A 3-STATE Outputs |
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B0–B15 |
B-to-A Data Inputs or |
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A-to-B 3-STATE Outputs |
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FACTä, Quiet Seriesä, FACT Quiet Seriesä and GTOä are trademarks of Fairchild Semiconductor Corporation.
Outputs STATE-3 with Transceiver Registered Bit-16 74ACTQ16543
© 1999 Fairchild Semiconductor Corporation |
DS010967.prf |
www.fairchildsemi.com |
74ACTQ16543
Connection Diagram
Pin Assignment for SSOP and TSSOP
Functional Description
The ACTQ16543 contains sixteen non-inverting transceivers with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins may be shorted together to obtain full 16-bit operation. The following description applies to each byte. For data flow from A to B, for example, the A-to-B Enable (CEABn) input must be LOW in order to enter data from A0–A15 or take data from B0–B15,
as indicated in the Data I/O Control Table. With CEABn
LOW, a LOW signal on the A-to-B Latch Enable (LEABn) input makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the LEABn signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEABn and OEABn both LOW, the 3-STATE B output buffers are active and reflect the data present at the output of the A latches. Control of data flow from B to A is similar, but using the CEBAn,
LEBAn and OEBAn inputs.
Data I/O Control Table
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Inputs |
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Latch Status |
Output |
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(Byte n) |
Buffers |
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n |
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n |
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CEAB |
LEAB |
OEAB |
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(Byte n) |
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H |
X |
X |
Latched |
High Z |
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X |
H |
X |
Latched |
— |
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L |
L |
X |
Transparent |
— |
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X |
X |
H |
— |
High Z |
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L |
X |
L |
— |
Driving |
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H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
A-to-B data flow shown; B-to-A flow control
is the same, except using CEBAn, LEBAn and OEBAn
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2 |
Logic Diagrams
Byte 1 (0:7)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Byte 2 (8:15)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74ACTQ16543
3 |
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