Fairchild Semiconductor 74F1071SCX, 74F1071SC, 74F1071MTCX, 74F1071MTC, 74F1071MSAX Datasheet
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October 1994
Revised August 1999
74F1071
18-Bit Undershoot/Overshoot Clamp and ESD Protection Device
General Description
The 74F1071 is an 18-bit undershoot/overshoot clamp which is designed to limit bus voltages and also to protect more sensitive devices from electrical overstress due to electrostatic discharge (ESD). The inputs of the device aggressively clamp voltage excursions nominally at 0.5V below and 7V above ground.
Features
■18-bit array structure in 20-pin package
■FASTâ Bipolar voltage clamping action
■Dual center pin grounds for min inductance
■Robust design for ESD protection
■Low input capacitance
■Optimum voltage clamping for 5V CMOS/TTL applications
Ordering Code:
Order Number |
Package Number |
Package Description |
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74F1071SC |
M20B |
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide |
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74F1071MSA |
MSA20 |
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide |
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74F1071MTC |
MTC20 |
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Note: Simplified Component Representation
FASTâ is a registered trademark of Fairchild Semiconductor Corporation.
Clamp Undershoot/Overshoot Bit-18 74F1071
© 1999 Fairchild Semiconductor Corporation |
DS011685 |
www.fairchildsemi.com |
74F1071
Absolute Maximum Ratings(Note 1)
Storage Temperature |
−65°C to +150°C |
Ambient Temperature under Bias |
−65°C to +125°C |
Junction Temperature under Bias |
−65°C to +150°C |
Input Voltage (Note 2) |
−0.5V to +6V |
Input Current (Note 2) |
−200 mA to +50 mA |
ESD (Note 3) |
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Human Body Model |
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(MIL-STD-883D method 3015.7) |
±10 kV |
IEC 801-2 |
±6 kV |
Machine Model (EIAJIC-121-1981) |
±2 kV |
DC Latchup Source Current |
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(JEDEC Method 17) |
±500 mA |
Package Power Dissipation @+70°C |
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SOIC Package |
800 mW |
Recommended Operating
Conditions
Free Air Ambient Temperature |
0°C to +70°C |
Reverse Bias Voltage |
0V to 5.25 VDC |
Thermal Resistance (θJA in Free Air) |
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SOIC Package |
100°C/W |
SSOP Package |
110°C/W |
Note 1: Absolute maximum ratings are DC values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Voltage ratings may be exceeded if current ratings and junction temperature and power consumption ratings are not exceeded.
Note 3: ESD Rating for Direct contact discharge using ESD Simulation Tester. Higher rating may be realized in the actual application.
DC Electrical Characteristics
Symbol |
Parameter |
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TA = +25°C |
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TA = 0°C to +70°C |
Units |
Conditions |
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Min |
Typ |
Max |
Min |
Max |
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IIH |
Input HIGH Current |
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1.5 |
10 |
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50 |
μA |
VIN = 5.25V; Untested Input @ GND |
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3 |
20 |
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100 |
VIN = 5.5V; Untested Input @ GND |
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VZ |
Reverse Voltage |
6.6 |
6.9 |
7.2 |
5.9 |
7.7 |
V |
IZ = 1 mA; Untested Inputs @ GND |
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7.1 |
7.5 |
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8.0 |
IZ = 50 mA; Untested Inputs @ GND |
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VF |
Forward Voltage |
−0.3 |
−0.6 |
−0.9 |
−0.3 |
−0.9 |
V |
IF = −18 mA; Untested Inputs @ 5V |
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−0.5 |
−1.1 |
−1.5 |
−0.5 |
−1.5 |
IF = −200 mA; Untested Inputs @ 5V |
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ICT |
Adjacent Input Crosstalk |
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3 |
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% |
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CIN |
Input Capacitance |
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25 |
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pF |
VBIAS = 0 VDC |
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(small signal @ 1 MHz) |
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13 |
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VBIAS = 5 VDC |
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www.fairchildsemi.com |
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