Fairchild Semiconductor 74F112SJX, 74F112SJ, 74F112SCX, 74F112SC, 74F112PC Datasheet
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April 1988
Revised July 1999
74F112
Dual JK Negative Edge-Triggered Flip-Flop
General Description
The 74F112 contains two independent, high-speed JK flipflops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. A LOW signal on SD or CD
prevents clocking and forces Q or Q HIGH, respectively.
Simultaneous LOW signals on SD and CD force both Q and
Q HIGH.
Asynchronous Inputs:
LOW input to SD sets Q to HIGH level
LOW input to CD sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q
and Q HIGH
Ordering Code:
Order Number |
Package Number |
Package Description |
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74F112SC |
M16A |
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow |
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74F112SJ |
M16D |
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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74F112PC |
N16E |
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols |
Connection Diagram |
IEEE/IEC
Flop-Flip Triggered-Edge Negative JK Dual 74F112
© 1999 Fairchild Semiconductor Corporation |
DS009472 |
www.fairchildsemi.com |
74F112
Unit Loading/Fan Out
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Pin Names |
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Description |
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U.L. |
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Input IIH/IIL |
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HIGH/LOW |
Output IOH/IOL |
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J1, J2, K1, K2 |
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Data Inputs |
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1.0/1.0 |
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20 μA/−0.6 mA |
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2 |
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Clock Pulse Inputs (Active Falling Edge) |
1.0/4.0 |
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20 μA/−2.4 mA |
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CP |
1, |
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CP |
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D2 |
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Direct Clear Inputs (Active LOW) |
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1.0/5.0 |
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20 μA/−3.0 mA |
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C |
D1, |
C |
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D2 |
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Direct Set Inputs (Active LOW) |
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1.0/5.0 |
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20 μA/−3.0 mA |
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S |
D1, |
S |
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−1 mA/20 mA |
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Q1, Q2, |
Q |
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Q |
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Outputs |
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50/33.3 |
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Truth Table |
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Inputs |
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Outputs |
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SD |
CD |
CP |
J |
K |
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Q |
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Q |
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L |
H |
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X |
X |
X |
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H |
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L |
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H |
L |
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X |
X |
X |
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L |
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H |
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L |
L |
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X |
X |
X |
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H |
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H |
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H |
H |
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h |
h |
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Q0 |
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Q |
0 |
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H |
H |
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l |
h |
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L |
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H |
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H |
H |
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h |
l |
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H |
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L |
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H |
H |
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l |
l |
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Q0 |
Q0 |
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H (h) = HIGH Voltage Level
L (l) = LOW Voltage Level X = Immaterial
= HIGH-to-LOW Clock Transition
Q0(Q0) = Before HIGH-to-LOW Transition of Clock
Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition.
Logic Diagram
(One Half Shown)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com |
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