Fairchild Semiconductor 74ACTQ16374SSCX, 74ACTQ16374SSC, 74ACTQ16374MTDX, 74ACTQ16374MTD, 74ACTQ16374CW Datasheet
June 1991
Revised November 1999
74ACTQ16374
16-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description
The ACTQ16374 contains sixteen non-inverting D-type flipflops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock (CP) and Output Enable (OE) are common to each byte and can be shorted together for full 16-bit operation.
The ACTQ16245 utilizes Fairchild Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO output control for superior performance.
Features
■Utilizes Fairchild FACT Quiet Series technology
■Guaranteed simultaneous switching noise level and dynamic threshold performance
■Guaranteed pin-to-pin output skew
■Buffered Positive edge-triggered clock
■Separate control logic for each byte
■16-bit version of the ACTQ374
■Outputs source/sink 24 mA
■Additional specs for Multiple Output Switching
■Output loadings specs for both 50 pF and 250 pF loads
Ordering Code:
Order Number |
Package Number |
Package Description |
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74ACTQ16374SSC |
MS48A |
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide |
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74ACTQ16374MTD |
MTD48 |
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide |
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Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Logic Symbol
Pin Descriptions
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Pin |
Description |
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Names |
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n |
Output Enable Input (Active LOW) |
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OE |
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CPn |
Clock Pulse Input |
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I0–I15 |
Inputs |
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O0–O15 |
Outputs |
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FACT , FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.
Outputs STATE-3 with Flop-Flip Type-D Bit-16 74ACTQ16374
© 1999 Fairchild Semiconductor Corporation |
DS010935 |
www.fairchildsemi.com |
74ACTQ16374
Functional Description
The ACTQ16374 consists of sixteen edge-triggered flipflops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Each byte has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each flip-flop will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CPn)
transition. With the Output Enable (OEn) LOW, the con- tents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operation of the OEn input does not affect the state of the flip-flops.
Logic Diagrams
Truth Tables
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Inputs |
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Outputs |
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CP1 |
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OE1 |
I0–I7 |
O0–O7 |
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L |
H |
H |
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L |
L |
L |
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L |
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L |
X |
(Previous) |
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X |
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H |
X |
Z |
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Inputs |
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Outputs |
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CP2 |
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OE2 |
I8–I15 |
O8–O15 |
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L |
H |
H |
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L |
L |
L |
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L |
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L |
X |
(Previous) |
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X |
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H |
X |
Z |
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H = HIGH Voltage Level
L = LOW Voltage Level
X= Immaterial
Z = HIGH Impedance
= LOW-to-HIGH Transition
Byte 1 (0:7)
Byte 2 (8:15)
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) |
− 0.5V to + 7.0V |
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DC Input Diode Current (IIK) |
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VI = |
− 0.5V |
− 20 mA |
VI = |
VCC + 0.5V |
+ 20 mA |
DC Output Diode Current (IOK) |
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VO = |
− 0.5V |
− 20 mA |
VO = |
VCC + 0.5V |
+ 20 mA |
DC Output Voltage (VO) |
− 0.5V to VCC + 0.5V |
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DC Output Source/Sink Current (IO) |
± 50 mA |
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DC VCC or Ground Current |
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per Output Pin |
± 50 mA |
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Storage Temperature |
− 65° C to + 150° C |
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Recommended Operating
Conditions
Supply Voltage (VCC) |
4.5V to 5.5V |
Input Voltage (VI) |
0V to VCC |
Output Voltage (VO) |
0V to VCC |
Operating Temperature (TA) |
− 40° C to + 85° C |
Minimum Input Edge Rate (∆ V/∆ t) |
125 mV/ns |
VIN from 0.8V to 2.0V |
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VCC @ 4.5V, 5.5V |
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Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics
Symbol |
Parameter |
VCC |
TA = + 25° C |
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TA = − 40° C to + 85° C |
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Conditions |
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(V) |
Typ |
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Guaranteed Limits |
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VIH |
Minimum HIGH |
4.5 |
1.5 |
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2.0 |
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2.0 |
V |
VOUT = |
0.1V |
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Input Voltage |
5.5 |
1.5 |
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2.0 |
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2.0 |
or VCC − |
0.1V |
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VIL |
Maximum LOW |
4.5 |
1.5 |
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0.8 |
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0.8 |
V |
VOUT = |
0.1V |
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Input Voltage |
5.5 |
1.5 |
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0.8 |
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0.8 |
or VCC − |
0.1V |
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VOH |
Minimum HIGH |
4.5 |
4.49 |
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4.4 |
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4.4 |
V |
IOUT = |
− |
50 µ A |
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Output Voltage |
5.5 |
5.49 |
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5.4 |
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5.4 |
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VIN = |
VIL or VIH |
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4.5 |
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3.86 |
3.76 |
V |
IOH = |
− |
24 mA |
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5.5 |
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4.86 |
4.76 |
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IOH = |
− 24 mA (Note 2) |
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VOL |
Maximum LOW |
4.5 |
0.001 |
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0.1 |
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0.1 |
V |
IOUT = |
50 µ A |
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Output Voltage |
5.5 |
0.001 |
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0.1 |
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0.1 |
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VIN = |
VIL or VIH |
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4.5 |
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0.36 |
0.44 |
V |
IOL = |
24 mA |
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5.5 |
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0.36 |
0.44 |
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IOL = |
24 mA (Note 2) |
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IOZ |
Maximum 3-STATE |
5.5 |
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± |
0.5 |
± |
5.0 |
µ A |
VI = |
VIL, VIH |
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Leakage Current |
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VO = |
VCC, GND |
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IIN |
Maximum Input Leakage Current |
5.5 |
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± |
0.1 |
± |
1.0 |
µ A |
VI = |
VCC, GND |
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ICCT |
Maximum ICC/Input |
5.5 |
0.6 |
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1.5 |
mA |
VI = |
VCC − 2.1V |
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ICC |
Maximum Quiescent Supply Current |
5.5 |
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8.0 |
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80.0 |
µ A |
VIN = |
VCC or GND |
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IOLD |
Minimum Dynamic |
5.5 |
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75 |
mA |
VOLD = |
1.65V Max |
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IOHD |
Output Current (Note 3) |
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− 75 |
mA |
VOHD = |
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3.85V Min |
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VOLP |
Quiet Output Maximum |
5.0 |
0.5 |
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0.8 |
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V |
Figure 1, Figure 2 |
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Dynamic VOL |
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(Note 5)(Note 6) |
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VOLV |
Quiet Output |
5.0 |
− 0.5 |
− 1.0 |
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V |
Figure 1, Figure 2 |
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Minimum Dynamic VOL |
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(Note 5)(Note 6) |
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VOHP |
Maximum Overshoot |
5.0 |
VOH + |
1.0 |
VOH + |
1.5 |
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V |
Figure 1, Figure 2 |
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(Note 4)(Note 6) |
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VOHV |
Minimum VCC Droop |
5.0 |
VOH − |
1.0 |
VOH − |
1.8 |
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V |
Figure 1, Figure 2 |
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(Note 4)(Note 6) |
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VIHD |
Minimum HIGH Dynamic Input Voltage Level |
5.0 |
1.7 |
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2.0 |
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V |
(Note 4)(Note 7) |
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VILD |
Maximum LOW Dynamic Input Voltage Level |
5.0 |
1.2 |
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0.8 |
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V |
(Note 4)(Note 7) |
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Note 2: All outputs loaded; thresholds associated with output under test.
Note 3: Maximum test duration 2.0 ms; one output loaded at a time.
Note 4: Worst case package.
Note 5: Maximum number of outputs that can switch simultaneously is n. (n − 1) outputs are switched LOW and one output held LOW.
Note 6: Maximum number of outputs that can switch simultaneously is n. (n − 1) outputs are switched HIGH and one output held HIGH.
Note 7: Maximum number of data inputs (n) switching. (n − 1) input switching 0V to 3V (ACTQ). Input under test switching 3V to threshold (VILD).
74ACTQ16374
3 |
www.fairchildsemi.com |
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