March 1990
Revised November 1998
74ACTQ841
Quiet Seriesä 10-Bit Transparent Latch with 3-STATE Outputs
General Description
The ACTQ841 bus interface latch is designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths or buses carrying parity. The 841 is a 10-bit transparent latch, a 10-bit version of the 373. The ACTQ841 utilizes Fairchild Quiet Seriesä technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTOä output control and undershoot corrector in addition to a split ground bus for superior performance.
Features
■Guaranteed simultaneous switching noise level and dynamic threshold performance
■Guaranteed pin-to-pin skew AC performance
■Inputs and outputs on opposite sides of package allow easy interface with microprocessors
■Improved latch-up immunity
■Outputs source/sink 24 mA
■Has TTL-compatible inputs
Ordering Code:
Order Number |
Package Number |
Package Description |
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74ACTQ841SC |
M24B |
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body |
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74ACTQ841SPC |
N24C |
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC, MS-100, 0.300” Wide |
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Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols |
Connection Diagram |
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Pin Assignment |
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for DIP and SOIC |
Pin Descriptions
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Pin Names |
Description |
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D0–D9 |
Data Inputs |
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O0–O9 |
3-STATE Outputs |
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Output Enable |
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OE |
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LE |
Latch Enable |
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FACTä, Quiet Seriesä, FACT Quiet Seriesä and GTOä are trademarks of Fairchild Semiconductor Corporation.
Outputs STATE-3 with Latch Transparent Bit-10 äSeries Quiet 74ACTQ841
© 1999 Fairchild Semiconductor Corporation |
DS010688.prf |
www.fairchildsemi.com |
74ACTQ841
Functional Description
The ACTQ841 consists of ten D-type latches with 3-STATE |
On the LE HIGH-to-LOW transition, the data that meets the |
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outputs. The flip-flops appear transparent to the data when |
setup and hold time is latched. Data appears on the bus |
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Latch Enable (LE) is HIGH. This allows asynchronous |
when the Output Enable |
(OE) |
is LOW. When |
OE |
is HIGH |
operation, as the output transition follows the data in transi- |
the bus output is in the high impedance state. |
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tion.
Function Table
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Inputs |
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Internal |
Output |
Function |
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LE |
D |
Q |
O |
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OE |
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X |
X |
X |
X |
Z |
High Z |
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H |
H |
L |
L |
Z |
High Z |
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H |
H |
H |
H |
Z |
High Z |
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H |
L |
X |
NC |
Z |
Latched |
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L |
H |
L |
L |
L |
Transparent |
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L |
H |
H |
H |
H |
Transparent |
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L |
L |
X |
NC |
NC |
Latched |
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H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
NC = No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) |
− 0.5V to + 7.0V |
DC Input Diode Current (IIK) |
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VI = − 0.5V |
− 20 mA |
VI = VCC + 0.5V |
+ 20 mA |
DC Input Voltage (VI) |
− 0.5V to VCC + 0.5V |
DC Output Diode Current (IOK) |
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VO = − 0.5V |
− 20 mA |
VO = VCC + 0.5V |
+ 20 mA |
DC Output Voltage (VO) |
− 0.5V to VCC + 0.5V |
DC Output Source |
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or Sink Current (IO) |
± 50 mA |
DC VCC or Ground Current |
± 50 mA |
per Output Pin (ICC or IGND) |
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Storage Temperature (TSTG) |
− 65°C to + 150°C |
DC Latch-Up Source |
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or Sink Current |
± 300 mA |
Junction Temperature (TJ) |
140°C |
PDIP |
Recommended Operating
Conditions
Supply Voltage (VCC) |
4.5V to 5.5V |
Input Voltage (VI) |
0V to VCC |
Output Voltage (VO) |
0V to VCC |
Operating Temperature (TA) |
− 40°C to + 85°C |
Minimum Input Edge Rate V/ t |
125 mV/ns |
VIN from 0.8V to 2.0V |
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VCC @ 4.5V, 5.5V |
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Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACTä circuits outside databook specifications.
DC Electrical Characteristics
Symbol |
Parameter |
VCC |
TA = +25°C |
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TA = − 40°C to +85°C |
Units |
Conditions |
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(V) |
Typ |
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Guaranteed Limits |
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VIH |
Minimum High Level |
4.5 |
1.5 |
2.0 |
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2.0 |
V |
VOUT = 0.1V |
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Input Voltage |
5.5 |
1.5 |
2.0 |
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2.0 |
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or VCC − 0.1V |
VIL |
Maximum Low Level |
4.5 |
1.5 |
0.8 |
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0.8 |
V |
VOUT = 0.1V |
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Input Voltage |
5.5 |
1.5 |
0.8 |
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0.8 |
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or VCC − 0.1V |
VOH |
Minimum High Level |
4.5 |
4.49 |
4.4 |
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4.4 |
V |
IOUT = − 50 μA |
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Output Voltage |
5.5 |
5.49 |
5.4 |
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5.4 |
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VIN = VIL or VIH |
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4.5 |
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3.86 |
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3.76 |
V |
IOH = − 24 mA |
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5.5 |
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4.86 |
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4.76 |
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IOH = − 24 mA (Note 2) |
VOL |
Maximum Low Level |
4.5 |
0.001 |
0.1 |
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0.1 |
V |
IOUT = 50 μA |
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Output Voltage |
5.5 |
0.001 |
0.1 |
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0.1 |
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VIN = VIL or VIH |
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4.5 |
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0.36 |
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0.44 |
V |
IOL = − 24 mA |
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5.5 |
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0.36 |
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0.44 |
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IOL = − 24 mA (Note 2) |
IIN |
Maximum Input |
5.5 |
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± 0.1 |
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± 1.0 |
μA |
VI = VCC, GND |
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Leakage Current |
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IOZ |
Maximum 3-STATE |
5.5 |
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± 0.5 |
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± 5.0 |
μA |
VI = VIL, VIH |
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Leakage Current |
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VO = VCC, GND |
ICCT |
Maximum ICC/Input |
5.5 |
0.6 |
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1.5 |
mA |
VI = VCC − 2.1V |
IOLD |
Minimum Dynamic |
5.5 |
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75 |
mA |
VOLD = 1.65V Max |
IOHD |
Output Current (Note 3) |
5.5 |
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−75 |
mA |
VOHD = 3.85V Min |
ICC |
Maximum Quiescent |
5.5 |
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8.0 |
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80.0 |
μA |
VIN = VCC or GND |
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Supply Current |
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VOLP |
Quiet Output |
5.0 |
1.1 |
1.5 |
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V |
Figure 1, Figure 2 |
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Maximum Dynamic VOL |
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(Note 4)(Note 5) |
VOLV |
Quiet Output |
5.0 |
−0.6 |
−1.2 |
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V |
Figure 1, Figure 2 |
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Minimum Dynamic VOL |
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(Note 4)(Note 5) |
VIHD |
Minimum High Level |
5.0 |
1.9 |
2.2 |
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V |
(Note 4)(Note 6) |
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Dynamic Input Voltage |
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VILD |
Maximum Low Level |
5.0 |
1.2 |
0.8 |
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V |
(Note 4)(Note 6) |
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Dynamic Input Voltage |
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Note 2: All outputs loaded; thresholds on input associated with output under test.
74ACTQ841
3 |
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