October 2001
Revised October 2001
74ALVC162374
Low Voltage 16-Bit D-Type Flip-Flop with 3.6V Tolerant Inputs and Outputs and 26Ω Series Resistors in Outputs
General Description
The ALVC162374 contains sixteen non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock (CP) and output enable (OE) are common to each byte and can be shorted together for full 16-bit operation.
The ALVC162374 is also designed with 26Ω series resistors in the outputs. This design reduces line noise in applications such as memory address drivers, clock drivers and bus transceivers/transmitters.
The 74ALVC162374 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O compatibility up to 3.6V.
The 74ALVC162374 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
Features
■1.65V–3.6V VCC supply operation
■3.6V tolerant inputs and outputs
■26Ω series resistors in outputs
■tPD (CLK to On)
3.9ns max for 3.0V to 3.6V VCC
5.3 ns max for 2.3V to 2.7V VCC
9.6ns max for 1.65V to 1.95V VCC
■Power-off high impedance inputs and outputs
■Supports live insertion and withdrawal (Note 1)
■Uses patented noise/EMI reduction circuitry
■Latchup conforms to JEDEC JED78
■ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number |
Package Number |
Package Descriptions |
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74ALVC162374T |
MTD48 |
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide |
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Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol |
Pin Descriptions |
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Pin Names |
Description |
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n |
Output Enable Input (Active LOW) |
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OE |
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CPn |
Clock Pulse Input |
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I0–I15 |
Inputs |
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O0–O15 |
Outputs |
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Flop-Flip Type-D Bit-16 Voltage Low 74ALVC162374
© 2001 Fairchild Semiconductor Corporation |
DS500688 |
www.fairchildsemi.com |
74ALVC162374
Connection Diagram |
Truth Tables |
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Inputs |
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Outputs |
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CP1 |
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OE1 |
I0–I7 |
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O0–O7 |
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L |
H |
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H |
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L |
L |
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L |
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L |
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L |
X |
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O0 |
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X |
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H |
X |
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Z |
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Inputs |
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Outputs |
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CP2 |
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OE2 |
I8–I15 |
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O8–O15 |
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L |
H |
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H |
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L |
L |
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L |
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L |
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L |
X |
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O0 |
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X |
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H |
X |
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Z |
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H |
= HIGH Voltage Level |
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L |
= LOW Voltage Level |
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X |
= Immaterial (HIGH or LOW, inputs may not float) |
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Z |
= High Impedance |
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O0 = Previous O0 before HIGH-to-LOW of CP |
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Functional Description
The 74ALVC162374 consists of sixteen edge-triggered flipflops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Each clock has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each flip-
Logic Diagram
flop will store the state of their individual I inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CPn) transition. With the Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance
state. Operations of the OEn input does not affect the state of the flip-flops.
Byte 1 (0:7)
Byte 2 (8:15)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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