April 1988
Revised November 1999
74F109
Dual JK Positive Edge-Triggered Flip-Flop
General Description |
Asynchronous Inputs: |
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The F109 consists of two high-speed, completely indepen- |
LOW input to |
S |
D sets Q to HIGH level |
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dent transition clocked JK flip-flops. The clocking operation |
LOW input to |
C |
D sets Q to LOW level |
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is independent of rise and fall times of the clock waveform. |
Clear and Set are independent of clock |
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The JK design allows operation as a D-type flip-flop (refer |
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Simultaneous LOW on CD and SD makes |
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to F74 data sheet) by connecting the J and K inputs. |
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both Q and Q HIGH |
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Ordering Code:
Order Number |
Package Number |
Package Description |
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74F109SC |
M16A |
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body |
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74F109SJ |
M16D |
16-Lead Small Outline Package (SOP), EIAJ TYPE 11, 5.3mm Wide |
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74F109PC |
N16E |
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols |
Connection Diagram |
IEEE/IEC
Flop-Flip Triggered-Edge Positive JK Dual 74F109
© 1999 Fairchild Semiconductor Corporation |
DS009471 |
www.fairchildsemi.com |
74F109
Truth Table
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Inputs |
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Outputs |
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SD |
CD |
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CP |
J |
K |
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Q |
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Q |
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L |
H |
X |
X |
X |
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H |
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L |
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H |
L |
X |
X |
X |
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H |
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L |
L |
X |
X |
X |
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H |
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H |
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H |
H |
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I |
I |
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L |
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H |
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H |
H |
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h |
I |
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Toggle |
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H |
H |
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I |
h |
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Q |
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Q |
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H |
H |
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h |
h |
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L |
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H |
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X |
X |
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Q |
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Q |
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H (h) = |
HIGH Voltage Level |
L (l) = |
LOW Voltage Level |
= |
LOW-to-HIGH Transition |
X = |
Immaterial |
Q0 (Q0) = Before LOW-to-HIGH Transition of Clock
Lower case letters indicate the state of the referenced output one setup time prior to the LOW-to-HIGH clock transition.
Unit Loading/Fan Out
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Pin Names |
Description |
U.L. |
Input IIH/IIL |
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HIGH/LOW |
Output IOH/IOL |
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J1, J2, |
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1, |
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2 |
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Data Inputs |
1.0/1.0 |
20 µ A/− 0.6 mA |
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K |
K |
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CP1, CP2 |
Clock Pulse Inputs (Active Rising Edge) |
1.0/1.0 |
20 µ A/− 0.6 mA |
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D2 |
Direct Clear Inputs (Active LOW) |
1.0/3.0 |
20 µ A/− 1.8 mA |
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C |
D1, |
C |
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D2 |
Direct Set Inputs (Active LOW) |
1.0/3.0 |
20 µ A/− 1.8 mA |
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S |
D1, |
S |
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− 1 mA/20 mA |
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Q1, Q2, |
Q |
1, |
Q |
2 |
Outputs |
50/33.3 |
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Block Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 1)
Storage Temperature |
− 65° C to + 150° C |
Ambient Temperature under Bias |
− 55° C to + 125° C |
Junction Temperature under Bias |
− 55° C to + 175° C |
VCC Pin Potential to |
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Ground Pin |
− 0.5V to + 7.0V |
Input Voltage (Note 2) |
− 0.5V to + 7.0V |
Input Current (Note 2) |
− 30 mA to + 5.0 mA |
Voltage Applied to Output |
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in HIGH State (with Vcc = 0V) |
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Standard Output |
− 0.5V to VCC |
3-STATE Output |
− 0.5V to + 5.5V |
Current Applied to Output |
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in LOW State (Max) |
twice the rated IOL (mA) |
Recommended Operating
Conditions
Free Air Ambient Temperature |
0° C to + 70° C |
Supply Voltage |
+ 4.5V to + 5.5V |
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol |
Parameter |
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Min |
Typ |
Max |
Units |
VCC |
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Conditions |
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VIH |
Input HIGH Voltage |
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2.0 |
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V |
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Recognized as a HIGH Signal |
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VIL |
Input LOW Voltage |
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0.8 |
V |
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Recognized as a LOW Signal |
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VCD |
Input Clamp Diode Voltage |
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− 1.2 |
V |
Min |
IIN = |
− 18 mA |
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VOH |
Output HIGH Voltage |
10% VCC |
2.5 |
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V |
Min |
IOH = |
− |
1 mA |
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5% VCC |
2.7 |
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IOH = |
− |
1 mA |
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VOL |
Output LOW Voltage |
10% VCC |
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0.5 |
V |
Min |
IOL = |
20 mA |
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IIH |
Input HIGH Current |
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5.0 |
µ A |
Max |
VIN = |
2.7V |
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IBVI |
Input HIGH Current Breakdown Test |
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7.0 |
µ A |
Max |
VIN = |
7.0V |
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ICEX |
Output HIGH Leakage Current |
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50 |
µ A |
Max |
VOUT = |
VCC |
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VID |
Input Leakage Test |
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4.75 |
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V |
0.0 |
IID = |
1.9 µ A |
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All Other Pins Grounded |
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IOD |
Output Leakage |
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3.75 |
µ A |
0.0 |
VIOD = |
150 mV |
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Circuit Current |
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All Other Pins Grounded |
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− 0.6 |
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VIN = |
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IIL |
Input LOW Current |
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mA |
Max |
0.5V (Jn, Kn) |
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− 1.8 |
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VIN = |
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mA |
Max |
0.5V (CDn, SDn) |
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IOS |
Output Short-Circuit Current |
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− 60 |
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− 150 |
mA |
Max |
VOUT = |
0V |
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ICC |
Power Supply Current |
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11.7 |
17.0 |
mA |
Max |
CP = |
0V |
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74F109
3 |
www.fairchildsemi.com |
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