Fairchild Semiconductor 74ACTQ74SJX, 74ACTQ74SJ, 74ACTQ74SCX, 74ACTQ74SC, 74ACTQ74PC Datasheet

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March 1993

Revised November 1999

74ACTQ74

Quiet Series Dual D-Type Positive Edge-Triggered Flip-Flop

General Description

The 74ACTQ74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input.

The ACTQ74 utilizes Fairchild Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector in addition to a split ground bus for superior performance.

Asynchronous Inputs:

LOW input to SD (Set) sets Q to HIGH level

LOW input to CD (Clear) sets Q to LOW level

Clear and Set are independent of clock

Simultaneous LOW on CD and SD makes

both Q and Q HIGH

Features

■ICC reduced by 50%

■Guaranteed simultaneous switching noise level and dynamic threshold performance

■Guaranteed pin-to-pin skew AC performance

■Improved latch-up immunity

■4 kV minimum ESD immunity

■TTL-compatible inputs

Ordering Code:

Order Number	Package Number	Package Description

74ACTQ74SC	M14A	14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

74ACTQ74SJ	M14D	14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74ACTQ74PC	N14A	14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering form.

Connection Diagram

Pin Descriptions

Pin Names

Description

D1, D2

Data Inputs

CP1, CP2

Clock Pulse Inputs

Direct Clear Inputs

D1,

Direct Set Inputs

D1,

Q1,

1, Q2,

Outputs

FACT , FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.

Type-D Dual Series Quiet 74ACTQ74

DS010920

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74ACTQ74

Truth Table

Logic Symbols

(Each Half)

Inputs

Outputs

H =

HIGH Voltage Level

L =

LOW Voltage Level

X =

Immaterial

LOW-to-HIGH Clock Transition

0) =

Q0(Q

Previous Q(Q) before LOW-to-HIGH Transition of Clock

IEEE/IEC

Block Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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Absolute Maximum Ratings(Note 1)

Supply Voltage (VCC)		− 0.5V to + 7.0V
DC Input Diode Current (IIK)
VI =	− 0.5V		− 20 mA
VI =	VCC + 0.5V		+ 20 mA
DC Input Voltage (VI)		− 0.5V to VCC + 0.5V
DC Output Diode Current (IOK)
VO =	− 0.5V		− 20 mA
VO =	VCC + 0.5V		+ 20 mA
DC Output Voltage (VO)		− 0.5V to VCC + 0.5V
DC Output Source
or Sink Current (IO)		±	50 mA
DC VCC or Ground Current
per Output Pin (ICC or IGND)		±	50 mA
Storage Temperature (TSTG)		− 65° C to + 150° C
DC Latch-Up Source or Sink Current		±	300 mA
Junction Temperature (TJ) PDIP			140° C

Recommended Operating

Conditions

Supply Voltage (V		)	4.5V to 5.5V
	CC
Input Voltage (VI)			0V to VCC
Output Voltage (VO)			0V to VCC
Operating Temperature (TA)			− 40° C to + 85° C
Minimum Input Edge Rate ∆ V/∆ t
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V			125 mV/ns

Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.

DC Electrical Characteristics

Symbol

Parameter

VCC

= + 25° C

TA = − 40° C to + 85° C

Units

Conditions

(V)

Typ

Guaranteed Limits

VIH

Minimum HIGH Level

4.5

1.5

2.0

VOUT =

0.1V

Input Voltage

5.5

1.5

2.0

or VCC −

0.1V

VIL

Maximum LOW Level

4.5

1.5

0.8

VOUT =

0.1V

Input Voltage

5.5

1.5

0.8

or VCC −

0.1V

VOH

Minimum HIGH Level

4.5

4.49

4.4

IOUT =

−

50 µ A

Output Voltage

5.5

5.49

5.4

4.5

3.86

3.76

VIN =

VIL or VIH

5.5

4.86

4.76

IOH = − 24 mA

IOH = − 24 mA (Note 2)

VOL

Maximum LOW Level

4.5

0.001

0.1

IOUT =

50 µ A

Output Voltage

5.5

0.001

0.1

4.5

0.36

0.44

VIN =

VIL or VIH

5.5

0.36

0.44

IOL = 24 mA

IOL = 24 mA (Note 2)

IIN

Maximum Input Leakage Current

5.5

0.1

1.0

µ A

VI =

VCC, GND

IOZ

Maximum 3-STATE

5.5

0.5

5.0

µ A

VI =

VIL, VIH

Leakage Current

VO =

VCC, GND

ICCT

Maximum ICC/Input

5.5

0.6

1.5

VI =

VCC − 2.1V

IOLD

Minimum Dynamic

5.5

VOLD =

1.65V Max

IOHD

Output Current (Note 2)

5.5

−

VOHD =

3.85V Min

ICC

Maximum Quiescent Supply Current

5.5

2.0

20.0

µ A

VIN =

VCC or GND

VOLP

Quiet Output Maximum

5.0

1.1

1.5

Figure 1, Figure 2

Dynamic VOL

(Note 4)(Note 5)

VOLV

Quiet Output Minimum

5.0

− 0.6

− 1.2

Figure 1, Figure 2

Dynamic VOL

(Note 4)(Note 5)

VIHD

Minimum HIGH Level Dynamic Input Voltage

5.0

1.9

2.2

(Note 4)(Note 6)

VILD

Maximum LOW Level Dynamic Input Voltage

5.0

1.2

0.8

(Note 4)(Note 6)

Note 2: All outputs loaded; thresholds on input associated with output under test.

Note 3: Maximum test duration 2.0 ms, one output loaded at a time.

Note 4: PDIP package.

Note 5: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND.

Note 6: Max number of data inputs (n) switching. (n − 1) inputs switching 0V to 3V. Input-under-test switching:

3V to threshold (VILD), 0V to threshold (VIHD), f =

1 MHz.

74ACTQ74

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