March 1990
Revised December 1998
74ACTQ843
Quiet Seriesä 9-Bit Transparent Latch with 3-STATE Outputs
General Description
The ACTQ843 bus interface latch is designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths. The ACTQ843 utilizes Fairchild FACT Quiet Seriesä technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTOä output control and undershoot corrector in addition to a split ground bus for superior performance.
Features
■Guaranteed simultaneous switching noise level and dynamic threshold performance
■Guaranteed pin-to-pin skew AC performance
■Inputs and outputs on opposite sides of package for easy interface with microprocessors
■Improved latch-up immunity
■Outputs source/sink 24 mA
■ACTQ843 has TTL-compatible inputs
■Functionally and pin-compatible to AMD’s AM29843
■3-STATE outputs for bus interfacing
Ordering Code:
Order Number |
Package Number |
Package Description |
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74ACTQ843SC |
M24B |
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body |
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74ACTQ843SPC |
N24C |
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide |
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Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols |
Connection Diagram |
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Pin Assignment for DIP and SOIC |
Pin Descriptions
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Pin Names |
Description |
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D0–D8 |
Data Inputs |
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O0–O8 |
Data Outputs |
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OE |
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Output Enable |
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LE |
Latch Enable |
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Clear |
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CLR |
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Preset |
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PRE |
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FACTä, Quiet Seriesä, FACT Quiet Seriesä and GTOä are trademarks of Fairchild Semiconductor Corporation.
Outputs STATE-3 with Latch Transparent Bit-9 äSeries Quiet 74ACTQ843
© 1999 Fairchild Semiconductor Corporation |
DS010689.prf |
www.fairchildsemi.com |
74ACTQ843
Functional Description
The ACTQ843 consists of nine D-type latches with 3- STATE outputs. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. This allows asynchronous operation, as the output transition follows the data in transition. On the LE HIGH-to-LOW transition, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state.
In addition to the LE and OE pins, the ACTQ843 has a Clear (CLR) pin and a Preset (PRE) pin. These pins are ideal for parity bus interfacing in high performance systems. When CLR is LOW, the outputs are LOW if OE is LOW. When CLR is HIGH, data can be entered into the
latch. When PRE is LOW, the outputs are HIGH if OE is LOW. Preset overrides CLR.
Function Table
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Inputs |
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Internal |
Outputs |
Function |
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LE |
D |
Q |
O |
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CLR |
PRE |
OE |
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H |
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H |
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H |
H |
L |
L |
Z |
High Z |
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H |
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H |
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H |
H |
H |
H |
Z |
High Z |
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H |
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H |
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H |
L |
X |
NC |
Z |
Latched |
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H |
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H |
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L |
H |
L |
L |
L |
Transparent |
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H |
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H |
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L |
H |
H |
H |
H |
Transparent |
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H |
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H |
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L |
L |
X |
NC |
NC |
Latched |
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H |
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L |
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L |
X |
X |
H |
H |
Preset |
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L |
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H |
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L |
X |
X |
L |
L |
Clear |
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L |
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L |
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L |
X |
X |
H |
H |
Preset |
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L |
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H |
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H |
L |
X |
L |
Z |
Clear/High Z |
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H |
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L |
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H |
L |
X |
H |
Z |
Preset/High Z |
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H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
NC = No Change
Logic Diagram
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) |
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−0.5V to +7.0V |
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DC Input Diode Current (IIK) |
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VI = −0.5V |
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−20 mA |
VI = VCC + 0.5V |
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+20 mA |
DC Input Voltage (VI) |
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−0.5V to VCC + 0.5V |
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DC Output Diode Current (I OK) |
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VO = −0.5V |
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−20 mA |
VO = VCC + 0.5V |
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+20 mA |
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DC Output Voltage (VO) |
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−0.5V to VCC + 0.5V |
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DC Output Source |
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or Sink Current (IO) |
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±50 mA |
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DC VCC or Ground Current |
±50 mA |
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per Output Pin (I |
CC |
or I |
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GND |
−65°C to +150°C |
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Storage Temperature (TSTG) |
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DC Latch-Up Source |
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or Sink Current |
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± 300 mA |
Junction Temperature (TJ) |
140°C |
PDIP |
Recommended Operating
Conditions
Supply Voltage (VCC) |
4.5V to 5.5V |
Input Voltage (VI) |
0V to VCC |
Output Voltage (VO) |
0V to VCC |
Operating Temperature (TA) |
−40°C to +85°C |
Minimum Input Edge Rate V/ t |
125 mV/ns |
VIN from 0.8V to 2.0V |
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VCC @ 4.5V, 5.5V |
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Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACTä circuits outside databook specifications.
DC Electrical Characteristics
Symbol |
Parameter |
VCC |
TA = +25°C |
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TA = −40°C to +85°C |
Units |
Conditions |
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(V) |
Typ |
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Guaranteed Limits |
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VIH |
Minimum HIGH Level |
4.5 |
1.5 |
2.0 |
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2.0 |
V |
VOUT = 0.1V |
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Input Voltage |
5.5 |
1.5 |
2.0 |
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2.0 |
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or VCC − 0.1V |
VIL |
Maximum LOW Level |
4.5 |
1.5 |
0.8 |
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0.8 |
V |
VOUT = 0.1V |
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Input Voltage |
5.5 |
1.5 |
0.8 |
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0.8 |
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or VCC − 0.1V |
VOH |
Minimum HIGH Level |
4.5 |
4.49 |
4.4 |
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4.4 |
V |
IOUT = −50 μA |
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Output Voltage |
5.5 |
5.49 |
5.4 |
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5.4 |
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VIN = VIL or VIH |
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4.5 |
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3.86 |
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3.76 |
V |
IOH = 24 mA |
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5.5 |
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4.86 |
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4.76 |
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I OH = 24 mA (Note 2) |
VOL |
Maximum LOW Level |
4.5 |
0.001 |
0.1 |
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0.1 |
V |
IOUT = 50 μA |
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Output Voltage |
5.5 |
0.001 |
0.1 |
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0.1 |
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VIN = VIL or VIH |
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4.5 |
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0.36 |
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0.44 |
V |
IOL = 24 mA |
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5.5 |
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0.36 |
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0.44 |
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IOL = 24 mA (Note 2) |
IIN |
Maximum Input |
5.5 |
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± 0.1 |
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± 1.0 |
μA |
VI = VCC, GND |
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Leakage Current |
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IOZ |
Maximum 3-STATE |
5.5 |
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± 0.5 |
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± 5.0 |
μA |
VI = VIL, VIH |
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Leakage Current |
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VO = VCC, GND |
ICCT |
Maximum ICC/Input |
5.5 |
0.6 |
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1.5 |
mA |
VI = VCC − 2.1V |
IOLD |
Minimum Dynamic |
5.5 |
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75 |
mA |
VOLD = 1.65V Max |
IOHD |
Output Current (Note 3) |
5.5 |
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−75 |
mA |
VOHD = 3.85V Min |
ICC |
Maximum Quiescent |
5.5 |
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8.0 |
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80.0 |
μA |
VIN = VCC |
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Supply Current |
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or GND |
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VOLP |
Quiet Output |
5.0 |
1.1 |
1.5 |
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V |
Figure 1, Figure 2 |
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Maximum Dynamic VOL |
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(Note 4)(Note 5) |
VOLV |
Quiet Output |
5.0 |
−0.6 |
−1.2 |
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V |
Figure 1, Figure 2 |
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Minimum Dynamic VOL |
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(Note 4)(Note 5) |
VIHD |
Minimum HIGH Level |
5.0 |
1.9 |
2.0 |
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V |
(Note 4)(Note 6) |
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Dynamic Input Voltage |
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VILD |
Maximum LOW Level |
5.0 |
1.2 |
0.8 |
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V |
(Note 4)(Note 6) |
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Dynamic Input Voltage |
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74ACTQ843
3 |
www.fairchildsemi.com |
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