Texas Instruments SMJ320C25-50FJ, SMJ320C25-50GB, SMJ320C25-GB, SMJ320C25FJ, SMJ320C25-50FD Datasheet

DMilitary Temperature Range

––55° C to 125° C

D100-ns or 80-ns Instruction Cycle Times

D544 Words of Programmable On-Chip Data RAM

D4K Words of On-Chip Program ROM

D128K Words of Data/Program Space

D16 Input and 16 Output Channels

D16-Bit Parallel Interface

DDirectly Accessible External Data Memory Space

–Global Data Memory Interface

D16-Bit Instruction and Data Words

D16 × 16-Bit Multiplier With a 32-Bit Product

D32-Bit ALU and Accumulator

DSingle-Cycle Multiply/Accumulate Instructions

D0 to 16-Bit Scaling Shifter

DBit Manipulation and Logical Instructions

DInstruction Set Support for Floating-Point Operations, Adaptive Filtering, and Extended-Precision Arithmetic

DBlock Moves for Data/Program Management

DRepeat Instructions for Efficient Use of Program Space

DEight Auxiliary Registers and Dedicated Arithmetic Unit for Indirect Addressing

DSerial Port for Direct Code Interface

DSynchronization Input for Synchronous Multiprocessor Configurations

DWait States for Communication to Slow-Off-Chip Memories/Peripherals

DOn-Chip Timer for Control Operations

DThree External Maskable User Interrupts

DInput Pin Polled by Software Branch Instruction

D1.6-µ m CMOS Technology

DProgrammable Output Pin for Signaling External Devices

SMJ320C25, SMJ320C25 50

DIGITAL SIGNAL PROCESSOR

SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001

DSingle 5-V Supply

DOn-Chip Clock Generator

DPackaging:

–68-Pin Leaded Ceramic Chip Carrier (FJ Suffix)

–68-Pin Ceramic Grid Array (GB Suffix)

–68-Pin Leadless Ceramic Chip Carrier (FD Suffix)

68-Pin FJ and FD Packages

(Top View)

					D8		D9		D10		D11		D12		D13		D14		D15								READY				CLKR CLKX				V		V
																																			CC		CC
	VSS		9			8		7		6		5		4		3		2		1			68 67 66 65 64 63 62 61
				10																																	60				IACK
	D7			11																																	59			MSC
	D6			12																																	58			CLKOUT1
	D5			13																																	57			CLKOUT2
	D4																																				56			XF
				14
	D3			15																																	55				HOLDA
	D2			16																																	54			DX
	D1			17																																	53			FSX
	D0			18																																	52			X2 CLKIN
	SYNC			19																																	51			X1
	INT0																																				50			BR
				20
	INT1			21																																	49				STRB
	INT2			22																																	48			R/W
	VCC			23																																	47			PS
	DR			24																																	46			IS
	FSR			25																																	45				DS
	A0			26																																	44			VSS
					27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
				V			A1		A2		A3		A4		A5		A6		A7		V		A8 A9 A10						A11 A12 A13						A14		A15
					SS																CC

68-Pin GB Package

(Top View)

1 2 3 4 5 6 7 8 9 10 11

A

B

C

D

E

F

G

H

J

K

L

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

	PRODUCTION DATA information is current as of publication date.	Copyright 2001, Texas Instruments Incorporated
	Products conform to specifications per the terms of Texas Instruments	On products compliant to MIL PRF 38535, all parameters are tested
	standard warranty. Production processing does not necessarily include
		unless otherwise noted. On all other products, production
	testing of all parameters.
		processing does not necessarily include testing of all parameters.
	POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443	1

SMJ320C25, SMJ320C25 50

DIGITAL SIGNAL PROCESSOR

SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001

description

This data sheet provides design documentation for the SMJ320C25 and the SMJ320C25-50 digital signal processor (DSP) devices in the SMJ320 family of VLSI digital signal processors and peripherals. The SMJ320 family supports a wide range of digital signal processing applications such as tactical communications, guidance, military modems, speech processing, spectrum analysis, audio processing, digital filtering, high-speed control, graphics, and other computation-intensive applications.

Differences between the SMJ320C25 and the SMJ320C25-50 are specifically identified, as in the following paragraph and in the parameter tables on pages 18 through 24 of this data sheet. When not specifically differentiated, the term SMJ320C25 is used to describe both devices.

The SMJ320C25 has a 100-ns instruction cycle time. The SMJ320C25-50 has an 80-ns instruction cycle time. With these fast instruction cycle times and their innovative memory configurations, these devices perform operations necessary for many real-time digital signal processing algorithms. Since most instructions require only one cycle, the SMJ320C25 is capable of executing 12.5 million instructions per second. On-chip data RAM of 544 16-bit words, on-chip program ROM of 4K words, direct addressing of up to 64K words of external data memory space and 64K words of external program memory space, and multiprocessor interface features for sharing global memory minimize unnecessary data transfers to take full advantage of the capabilities of the instruction set.

Table 1. PGA/CLCC/LCCC Pin Assignments

FUNCTION

PIN

FUNCTION

PIN

FUNCTION

PIN

FUNCTION

PIN

FUNCTION

PIN

FUNCTION

PIN

A0

K1/26

A12

K8/40

D2

E1/16

D14

A5/3

INT2

H1/22

VCC

H2/23

A1

K2/28

A13

L9/41

D3

D2/15

D15

B6/2

J11/46

VCC

L6/35

IS

A2

L3/29

A14

K9/42

D4

D1/14

DR

J1/24

A6/1

VSS

B1/10

MP/MC

A3

K3/30

A15

L10/43

D5

C2/13

DS

K10/45

C10/59

VSS

K11/44

MSC

A4

L4/31

B7/68

D6

C1/12

DX

E11/54

J10/47

VSS

L2/27

BI0

PS

A5

K4/32

G11/50

D7

B2/11

FSR

J2/25

READY

B8/66

XF

D11/56

BR

A6

L5/33

CLKOUT1

C11/58

D8

A2/9

FSX

F10/53

A8/65

X1

G10/51

RS

A7

K5/34

CLKOUT2

D10/57

D9

B3/8

A7/67

H11/48

X2/CLKIN

F11/52

HOLD

R/W

A8

K6/36

CLKR

B9/64

D10

A3/7

E10/55

H10/49

HOLDA

STRB

A9

L7/37

CLKX

A9/63

D11

B4/6

B11/60

F2/19

IACK

SYNC

A10

K7/38

D0

F1/18

D12

A4/5

G1/20

VCC

A10/61

INT0

A11

L8/39

D1

E2/17

D13

85/4

G2/21

VCC

B10/62

INT1

SMJ320 is a trademark of Texas Instruments Incorporated.

2	POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

SMJ320C25, SMJ320C25 50

DIGITAL SIGNAL PROCESSOR

SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001

Terminal Functions

SIGNALS

I/O/Z†

DEFINITION

VCC

I

5-V supply pins

VSS

I

Ground pins

X1

0

Output from internal oscillator for crystal

X2/CLKIN

I

Input to internal oscillator from crystal or external clock

CLKOUT1

0

Master clock output (crystal or CLKIN frequency/4)

CLKOUT2

0

A second clock output signal

D15–D0

I/O/Z

16-bit data bus D15 (MSB) through D0 (LSB). Multiplexed between program, data, and I/0 spaces.

A15–A0

O/Z

16-bit address bus A15 (MSB) through A0 (LSB)

O/Z

Program, data, and I/O space select signals

PS,DS,IS

O/Z

Read / write signal

R/W

O/Z

Strobe signal

STRB

I

Reset input

RS

I

External user interrupt inputs

INT2–INT0

I

Microprocessor/microcomputer mode select pin

MP/MC

0

Microstate complete signal

MSC

0

Interrupt acknowledge signal

IACK

READY

I

Data ready input. Asserted by external logic when using slower devices to indicate that the current bus

transaction is complete.

Bus request signal. Asserted when the SMJ320C25 requires access to an external global data memory

BR

0

space.

XF

0

External flag output (latched software-programmable signal)

Hold input. When asserted, SMJ320C25 goes into an idle mode and places the data, address, and

HOLD

1

control lines in the high-impedance state.

0

Hold acknowledge signal

HOLDA

I

Synchronization input

SYNC

I

Branch control input. Polled by BIOZ instruction

BIO

DR

I

Serial data receive input

CLKR

I

Clock for receive input for serial port

FSR

I

Frame synchronization pulse for receive input

DX

O/Z

Serial data transmit output

CLKX

I

Clock for transmit output for serial port

FSX

I/O/Z

Frame synchronization pulse for transmit. Configurable as either an input or an output.

† I/O/Z denotes input/output/high-impedance state.

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3

SMJ320C25, SMJ320C25 50

DIGITAL SIGNAL PROCESSOR

SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001

block diagram

SYNC								Program Bus
IS
			X1	X2/CLKIN	CLKOUT1 CLKOUT2			16
DS
PS						16			16	16
R/W						PFC(16)				QIR(16)
										IR(16)
STRB						16
READY										STO(16)
							MUX
BR		Controller				16
										IFR(6)
HOLDA
XF							16	16		RPTC(8)
HOLD
MSC			MCS(16)				PC(16)					DR
BIO
												CLKR
RS
						16	16	16				FSR
IACK												DX
					Address		Stack					CLKX
MP/MC			16						16			FSX
		3						16
INT(2-0)					Program		(8 x 16)			RSR(16)
			16		ROM/					XSR(16)
	16				EPROM				16	DRR(16)
A15-A0	MUX				(4096 ×	16)			16
										DXR(16)
					Instruction				16	TIM(16)
						16			16	PRD(16)
									6
										IMR(6)
	16					16
									8	GREG(8)
D15-D0	MUX				16
									16
								16
						Data Bus				Program Bus
		16										16
			16		16		9		16	16	16
	3
					AR0(16)
								7 LSB		TR(16)
					AR1(16)						MUX
		3						From IR
	ARP(3)				AR2(16)		DP(9)			Multiplier	16
					AR3(16)
								Shifter(0-16)
					AR4(16)		9
	3				AR5(16)					PR(32)
					AR6(16)
					AR7(16)		16		32	32
	ARB(3)
										Shifter(-6, 0, 1, 4)
						16		16		32
	3						MUX
					ARAU(16)
						16				MUX
							16			32
			MUX				MUX
			16				16	32		ALU(32)

32

Block B2

DATA/PROG

(32 × 16)

RAM (256 × 16)

Data RAM

Block B0

C

ACCH(16)

ACCL(16)

Block B1

16

32

(256 × 16)

MUX

Shifters (0-7)†

16

16

16

16

LEGEND:

Data Bus

ACCH

=

Accumulator high

IFR

=

Interrupt flag register

PC

=

Program counter

ACCL

=

Accumulator low

IMR

=

Interrupt mask register

PFC

=

Prefetch counter

ALU

=

Arithmetic logic unit

IR

=

Instruction register

RPTC

=

Repeat instruction counter

ARAU

=

Auxiliary register arithmetic unit

MCS

=

Microcall stack

GREG

=

Global memory allocation register

ARB

=

Auxiliary register pointer buffer

QIR

=

Queue instruction register

RSR

=

Serial port receive shift register

ARP

=

Auxiliary register pointer

PR

=

Product register

XSR

=

Serial port transmit shift register

DP

=

Data memory page pointer

PRD

=

Period register for timer

AR0-AR7

=

Auxiliary registers

DRR

=

Serial port data receive register

TIM

=

Timer

ST0, ST1

=

Status registers

DXR

=

Serial port data transmit register

TR

=

Temporary register

C

=

Carry bit

4	POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

SMJ320C25, SMJ320C25 50

DIGITAL SIGNAL PROCESSOR

SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001

architecture

The SMJ320C25 increases performance of DSP algorithms through innovative additions to the SMJ320 architecture. Increased throughput on the SMJ320C25 for many DSP applications is accomplished by means of single-cycle multiply/accumulate instructions with a data move option, eight auxiliary registers with a dedicated arithmetic unit, and faster I/O necessary for data-intensive signal processing.

The architectural design of the SMJ320C25 emphasizes overall speed, communication, and flexibility in processor configuration. Control signals and instructions provide floating-point support, block-memory transfers, communication to slower off-chip devices, and multiprocessing implementations.

Two large on-chip RAM blocks, configurable either as separate program and data spaces or as two contiguous data blocks, provide increased flexibility in system design. Programs of up to 4K words can be masked into the internal program ROM. The remainder of the 64K-word program memory space is located externally. Large programs can execute at full speed from this memory space. Programs can also be downloaded from slow external memory to high-speed on-chip RAM. A total of 64K data memory address space is included to facilitate implementation of DSP algorithms. The VLSI implementation of the SMJ320C25 incorporates all of these features as well as many others, such as a hardware timer, serial port, and block data transfer capabilities.

32-bit ALU/accumulator

The SMJ320C25 32-bit arithmetic logic unit (ALU) and accumulator perform a wide range of arithmetic and logical instructions, the majority of which execute in a single clock cycle. The ALU executes a variety of branch instructions dependent on the status of the ALU or a single bit in a word. These instruction provide the following capabilities:

DBranch to an address specified by the accumulator

DNormalize fixed-point numbers contained in the accumulator

DTest a specified bit of a word in data memory.

One input to the ALU is always provided from the accumulator, and the other input can be provided from the product register (PA) of the multiplier or the input scaling shifter which has fetched data from the RAM on the data bus. After the ALU has performed the arithmetic or logical operations, the result is stored in the accumulator.

The 32-bit accumulator is split into two 16-bit segments for storage in data memory. Additional shifters at the output of the accumulator perform shifts while the data is being transferred to the data bus for storage. The contents of the accumulator remain unchanged.

scaling shifter

The SMJ320C25 scaling shifter has a 16-bit input connected to the data bus and a 32-bit output connected to the ALU. The scaling shifter produces a left shift of 0 to 16 bits on the input data, as programmed in the instruction. The LSBs of the output are filled with zeroes, and the MSBs can be either filled with zeroes or sign-extended, depending upon the status programmed into the SXM (sign-extension mode) bit of status register ST1.

16 X 16-bit parallel multiplier

The SMJ320C25 has a 16 x 16-bit hardware multiplier, which is capable of computing a signed or unsigned 32-bit product in a single machine cycle. The multiplier has the following two associated registers:

DA 16-bit temporary register (TR) that holds one of the operands for the multiplier, and

DA 32-bit product register (PR) that holds the product.

Incorporated into the SMJ320C25 instruction set are single-cycle multiply/accumulate instruction that allow both operands to be processed simultaneously. The data for these operations can reside anywhere in internal or external memory and can be transferred to the multiplier each cycle via the program and data buses.

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5

SMJ320C25, SMJ320C25 50

DIGITAL SIGNAL PROCESSOR

SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001

16 X 16-bit parallel multiplier (continued)

Four product shift modes are available at the product register (PR) output that are useful when performing multiply/accumulate operations, fractional arithmetic, or justifying fractional products.

timer

The SMJ320C25 provides a memory-mapped 16-bit timer for control operations. The on-chip timer (TIM) register is a down counter that is continuously clocked by CLKOUT1. A timer interrupt (TINT) is generated every time the timer decrements to zero. The timer is reloaded with the value contained in the period (PRD) register within the next cycle after it reaches zero so that interrupts can be programmed to occur at regular intervals of PRD + 1 cycles of CLKOUT1.

memory control

The SMJ320C25 provides a total of 544 16-bit words of on-chip data RAM, divided into three separate blocks (B0, B1, and B2). Of the 544 words, 288 words (blocks B1 and B2) are always data memory, and 256 words (block B0) are programmable as either data or program memory. A data memory size of 544 words allows the SMJ320C25 to handle a data array of 512 words (256 words if on-chip RAM is used for program memory), while still leaving 32 locations for intermediate storage. When using block B0 as program memory, instructions can be downloaded from external program memory into on-chip RAM and then executed.

When using on-chip program RAM, ROM, or high-speed external program memory, the SMJ320C25 runs at full speed without wait states. However, the READY line can be used to interface the SMJ320C25 to slower, less-expensive external memory. Downloading programs from slow off-chip memory to on-chip program RAM speeds processing while cutting system costs.

The SMJ320C25 provides three separate address states for program memory, data memory, and I/O. The on-chip memory is mapped into either the 64K-word data memory or program memory space, depending upon the memory configuration. The CNF0 (configure block B0 as data memory) and CNFP (configure block B0 as program memory) instruction allow dynamic configuration of the memory maps through software. Regardless of the configuration, the user can still execute from external program memory.

The SMJ320C25 has six registers which are mapped into the data memory space: a serial port data receive register, serial port data transmit register, timer register, period register, interrupt mask register, and global memory allocation register.

6	POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

SMJ320C25, SMJ320C25 50

DIGITAL SIGNAL PROCESSOR

SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001

memory control (continued)

Program

0(0000h)

Interrupts

and Reserved (External)

31(001Fh) 32(0020h )

External

65,535(FFFFh)

If MP/MC = 1

(Microprocessor Mode)

Program

0(0000h)

Interrupts

and Reserved (External)

31(001Fh) 32(0020h )

External

65,279(0FEFFh)

65,280(0FF00h)

On-Chip

Block B0

65,535(0FFFFh)

If MP/MC = 1

(Microprocessor Mode)

	Program					Data
0(0000h)					0(0000h)
	Interrupts					On-Chip
	and Reserved
						Memory-Mapped
	(On-Chip
						Registers
	ROM/EPROM)				5(0005h)
31(001Fh)
					6(0006h)
32(0020h )						Reserved	Page 0
	On-Chip
4015(0FAFh)	ROM/EPROM				95(005Fh)
					96(0060h )
4016(0FB0h)						On-Chip
					127(007Fh)	Block B2
	Reserved
					128(0080h)
4095(0FFFh)						Reserved	Pages 1-3
4096(1000h)
					511(01FFh)
					512(0200h)	On-Chip	Pages 4-5
					767(02FFh)	Block B0
					768(0300h)
	External					On-Chip	Pages 6 -7
						Block B1
					1023(03FFh)
					1024(0400h)
						External	Pages 8 -511
65,535(0FFFFh)					65,535(0FFFFh)
	If MP/MC		= 0
	(Microcomputer Mode)
(a) Memory Maps After a CNFD Instruction

	Program				Data
0(0000h)	Interrupts			0(0000h)	On-Chip
	and Reserved
					Memory-Mapped
	(On-Chip
					Registers
	ROM/EPROM)
31(001Fh)				5(0005h)
32(0020h )	On-Chip			6(0006h)		Page 0
					Reserved
	ROM/EPROM
4015(0FAFh)				95(005Fh)
4016(0FB0h)	Reserved			96(0060h )	On-Chip
4095(0FFFh)					Block B2
4096(1000h)				127(007Fh)
				128(0080h)	Reserved	Pages 1-3
				511(01FFh)
				512(0200h)	Does Not
						Pages 4-5
					Exist
				767(02FFh)
	External
				768(0300h)	On-Chip
					Block B1	Pages 6 -7
				1023(03FFh)
				1024(0400h)
65,279(0FEFFh)					External	Pages 8 -511
65,280(0FF00h)
	On-Chip
65,535(0FFFFh)	Block B0			65,535(0FFFFh)

If MP/MC = 0

(Microcomputer Mode)

(b) Memory Maps After a CNFP Instruction

Figure 1. Memory Maps

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7

SMJ320C25, SMJ320C25 50

DIGITAL SIGNAL PROCESSOR

SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001

interrupts and subroutines

The SMJ320C25 has three external maskable user interrupts INT2–INT0, available for external devices that interrupt the processor. Internal interrupts are generated by the serial port (RINT and XINT), by the timer (TINT), and by the software interrupt (TRAP) instruction. Interrupts are prioritized with reset (RS) having the highest priority and the serial port transmit interrupt (XINT) having the lowest priority. All interrupt locations are on two-word boundaries so that branch instruction can be accommodated in those locations if desired.

A built-in mechanism protects multicycle instructions from interrupts. If an interrupt occurs during a multicycle instruction, the interrupt is not processed until the instruction is completed. This mechanism applies both to instructions that are repeated or become multicycle due to the READY signal.

external interface

The SMJ320C25 supports a wide range of system interfacing requirements. Program, data, and I/O address spaces provide interface to memory and I/O. thus maximizing system throughout. I/O design is simplified by having I/O treated the same way as memory. I/O devices are mapped into the I/O address space using the processor’s external address and data buses in the same manner as memory-mapped devices. Interface to memory and I/O devices of varying speeds is accomplished by using the READY line. When transitions are made with slower devices, the SMJ320C25 processor waits until the other device completes its function and signals the processor via the READY line. Then, the SMJ320C25 continues execution.

A full-duplex serial port provides communication with serial devices, such as codecs, serial A/D converters, and other serial systems. The interface signals are compatible with codecs and many other serial devices with a minimum of external hardware. The serial port can also be used for intercommunication between processors in multiprocessing applications.

The serial port has two memory-mapped registers: the data transmit register (DXR) and the data receive register (DRR). Both registers operate in either the byte mode or 16-bit word mode, any can be accessed in the same manner as any other data memory location. Each register has an external clock, a framing synchronization pulse, and associated shift registers. One method of multiprocessing can be implemented by programming one device to transmit while the others are in the receive mode.

multiprocessing

The flexibility of the SMJ320C25 allows configurations to satisfy a wide range of system requirements. The SMJ320C25 can be used as follows:

DA standalone processor

DA multiprocessor with devices in parallel

DA slave/host multiprocessor with global memory space

DA peripheral processor interfaced via processor-controlled signals to another device.

For multiprocessing applications, the SMJ320C25 has the capability of allocating global data memory space and communicating with that space via the BR (bus request) and READY control signals. Global memory is data memory shared by more than one processor. Global data memory access must be arbitrated. The 8-bit memory-mapped GREG (global memory allocation register) specifies part of the SMJ320C25s data memory as global external memory. The contents of the register determine the size of the global memory space. If the current instruction addresses an operand within that space, BR is asserted to request control of the bus. The length of the memory cycle is controlled by the READY line.

The SMJ320C25 supports DMA (direct memory access) to its external program/data memory using the HOLD and HOLDA signals. Another processor can take complete control of the SMJ320C25s external memory by asserting HOLD low. This causes the SMJ320C25 to place its address, data, and control lines in a high-impedance state, and assert HOLDA. Program execution from on-chip memory can proceed concurrently while the device is in the hold mode.

8	POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

SMJ320C25, SMJ320C25 50

DIGITAL SIGNAL PROCESSOR

SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001

instruction set

The SMJ320C25 microprocessor implements a numeric-intensive signal processing operations multiprocessing and high-speed control.

comprehensive instruction set that supports both as well as general-purpose applications, such as

For maximum throughput, the next instruction is prefetched while the current one is being executed. Since the same data lines are used to communicate to external data/program or I/O space, the number of cycles may vary depending upon whether the next data operand fetch is from internal or external program memory. Highest throughput is achieved by maintaining data memory on-chip and using either internal or fast external program memory.

addressing modes

The SMJ320C25 instruction set provides three memory addressing modes: direct, indirect, and immediate addressing.

Both direct and indirect addressing can be used to access data memory. In direct addressing, seven bits of the instruction word are concatenated with the nine bits of the data memory page pointer to form the 16-bit data memory address. Indirect addressing accesses data memory through the eight auxiliary registers. In immediate addressing, the data is based on a portion of the instruction word(s).

In direct memory addressing, the instruction word contains the lower seven bits of the data memory address. This field is concatenated with the nine bits of the data memory page pointer to form the full 16-bit address. Thus, memory is paged in the direct addressing mode with a total of 512 pages, each page containing 128 words.

Eight auxiliary register (AR0–AR7) provide flexible and powerful indirect addressing. To select a specific auxiliary register, the Auxiliary Register Pointer (ARP) is loaded with a value from 0 through 7 for AR0–AR7, respectively.

There are seven types of indirect addressing: auto-increment or auto-decrement, post-indexing by either adding or subtracting the contents of AR0, or single indirect addressing with no increment or decrement and bit-reversal addressing (used in FFTs) with increment or decrement. All operations are performed on the current auxiliary register in the same cycle as the original instruction, followed by anew ARP value being loaded.

repeat feature

A repeat feature, used with instructions such as multiply/accumulates, block moves, I/O transfers, and table read/writes, allows a single instruction to be performed up to 256 times. The repeat counter (RPTC) is loaded with either a data memory value (RPT instruction) or an immediate value (RPTK instruction) .The value of this operand is one less than the number of times that the next instruction is executed. Those instructions that are normally multicycle are pipelined when using the repeat feature, and effectively become single-cycle instructions.

instruction set summary

Table 1 lists the symbols and abbreviations used in Table 1, the instruction set summary, Table 2 consists primarily of single-cycle,single-word instructions. Infrequently used branch, I/O, and CALL instructions are multicycle. The instruction set summary is arranged according to function and alphabetized within each functional grouping.

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SMJ320C25, SMJ320C25 50

DIGITAL SIGNAL PROCESSOR

SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001

instruction set summary (continued)

	Table 1. Instruction Symbols
SYMBOL	MEANING
B	4-bit field specifying a bit code
CM	2-bit field specifying compare mode
D	Data memory address field
F0	Format status bit
M	Addressing mode bit
K	Immediate operand field
PA	Port address (PA0–PA15 are predefined assembler symbols equal to 0 through 15, respectively)
PM	2-bit field specifying P register output shift code
R	3-bit operand field specifying auxiliary register
S	4-bit left-shift code
X	3-bit accumulator left-shift field

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									SMJ320C25, SMJ320C25 50
								DIGITAL SIGNAL PROCESSOR
						SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
	Table 2. SMJ320C25 Instruction Set Summary
	ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS
MNEMONIC	DESCRIPTION	NO.					INSTRUCTION BIT CODE
		WORDS
			15	14	13	12	11		10			9	8		7		6	5	4		3			2	1	0
ABS	Absolute value of accumulator	1	1	1	0	0	1		1			1	0		0		0	0	1		1			0	1	1
ADD	Add to accumulator with shift	1	0	0	0	0					S				M								D
ADDC‡	Add to accumulator with carry	1	0	1	0	0	0		0			1	1		M								D
ADDH	Add to high accumulator	1	0	1	0	0	1		0			0	0		M								D
ADDK‡	Add to accumulator short immediate	1	1	1	0	0	1		1			0	0								K
ADDS	Add to low accumulator with sign	1	0	1	0	0	1		0			0	1		M								D
	extension suppressed
ADDT	Add to accumulator with shift specified by	1	0	1	0	0	1		0			1	0		M								D
	T register
ADLK†	Add to accumulator long immediate with shift	2	1	1	0	1					S				0		0	0	0		0			0	1	0
AND	AND with accumulator	1	0	1	0	0	1		1			1	0		M								D
ANDK†	AND immediate with accumulator with shift	2	1	1	0	1					S				0		0	0	0		0			1	0	0
CMPL†	Complement accumulator	1	1	1	0	0	1		1			1	0		0		0	1	0		0			1	1	1
LAC	Load accumulator with shift	1	0	0	1	0					S				M								D
LACK	Load accumulator immediate short			1	0	0	1		0			1	0								K
		1	1
LACT†	Load accumulator with shift specified by	1	0	1	0	0	0		0			1	0		M								D
	T register
LALK†	Load accumulator long immediate with shift	2	1	1	0	1					S				0		0	0	0		0			0	0	1
NEG†	Negate accumulator	1	1	1	0	0	1		1			1	0		0		0	1	0		0			0	1	1
NORM†	Normalize contents of accumulator	1	1	1	0	0	1		1			1	0		1								D
OR	OR with accumulator	1	0	1	0	0	1		1			0	1		M								D
ORK†	OR immediate with accumulator with shift	2	1	1	0	1					S				0		0	0	0		0			1	0	1
ROL‡	Rotate accumulator left	1	1	1	0	0	1		1			1	0		0		0	1	1		0			1	0	0
ROR‡	Rotate accumulator right	1	1	1	0	0	1		1			1	0		0		0	1	1		0			1	0	1
SACH	Store high accumulator with shift	1	0	1	1	0	1					X			M								D
SACL	Store low-order accumulator with shift	1	0	1	1	0	0					X			M								D
SBLK†	Subtract from accumulator long immediate	2	1	1	0	1					S				0		0	0	0		0			0	1	1
	with shift
SFL†	Shift accumulator left	1	1	1	0	0	1		1			1	0		0		0	0	1		1			0	0	0
SFR†	Shift accumulator right	1	1	1	0	0	1		1			1	0		0		0	0	1		1			0	0	1
SUB	Subtract from accumulator with shift	1	0	0	0	1					S				M								D
SUBB‡	Subtract from accumulator with borrow	1	0	1	0	0	1		1			1	1		M								D
SUBC	Conditional subtract	1	0	1	0	0	0		1			1	1		M								D
SUBH	Subtract from high accumulator	1	0	1	0	0	0		1			0	0		M								D
SUBK‡	Subtract from accumulator short immediate	1	1	1	0	0	1		1			0	1								K
SUBS	Subtract from low accumulator with sign	1	0	1	0	0	0		1			0	1		M								D
	extension suppressed
† These instructions are not included in the TMS320C1x instruction set.
‡ These instructions are not included in the TMS32020 instruction set.

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