MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual 2-Wide 2-3-Input
OR-AND/OR-AND Gate
The MC10H117 dual 2±wide 2±3±input OR±AND/OR±AND±Invert gate is a general purpose logic element designed for use in data control, such as digital multiplexing or data distribution. Pin 9 is common to both gates. This MECL 10H part is a functional/pinout duplication of the standard MECL 10K family part, with 100% improvement in propagation delay, and no increase in power±supply current.
•Propagation Delay, 1.0 ns Typical
•Power Dissipation 100 mW/Gate Typical (same as MECL 10K)
•Improved Noise Margin 150 mV (Over Operating Voltage and Temperature Range)
•Voltage Compensated
•MECL 10K±Compatible
MAXIMUM RATINGS
Characteristic |
Symbol |
Rating |
Unit |
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Power Supply (VCC = 0) |
VEE |
±8.0 to 0 |
Vdc |
Input Voltage (VCC = 0) |
VI |
0 to VEE |
Vdc |
Output Current Ð Continuous |
Iout |
50 |
mA |
Ð Surge |
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100 |
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Operating Temperature Range |
TA |
0 to +75 |
°C |
Storage Temperature Range Ð Plastic |
Tstg |
±55 to +150 |
°C |
Ð Ceramic |
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±55 to +165 |
°C |
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ELECTRICAL CHARACTERISTICS (VEE = ±5.2 V ±5%) (See Note)
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0° |
25° |
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75° |
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Characteristic |
Symbol |
Min |
Max |
Min |
Max |
Min |
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Max |
Unit |
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Power Supply Current |
IE |
Ð |
29 |
Ð |
26 |
Ð |
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29 |
mA |
Input Current High |
IinH |
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μA |
Pins 4, 5, 12, 13 |
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Ð |
465 |
Ð |
275 |
Ð |
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275 |
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Pins 6, 7, 10, 11 |
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Ð |
545 |
Ð |
320 |
Ð |
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320 |
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Pin 9 |
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Ð |
710 |
Ð |
415 |
Ð |
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415 |
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Input Current Low |
IinL |
0.5 |
Ð |
0.5 |
Ð |
0.3 |
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Ð |
μA |
High Output Voltage |
VOH |
±1.02 |
±0.84 |
±0.98 |
±0.81 |
±0.92 |
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±0.735 |
Vdc |
Low Output Voltage |
VOL |
±1.95 |
±1.63 |
±1.95 |
±1.63 |
±1.95 |
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±1.60 |
Vdc |
High Input Voltage |
VIH |
±1.17 |
±0.84 |
±1.13 |
±0.81 |
±1.07 |
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±0.735 |
Vdc |
Low Input Voltage |
VIL |
±1.95 |
±1.48 |
±1.95 |
±1.48 |
±1.95 |
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±1.45 |
Vdc |
AC PARAMETERS |
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Propagation Delay |
tpd |
0.45 |
1.35 |
0.45 |
1.35 |
0.5 |
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1.5 |
ns |
Rise Time |
tr |
0.5 |
1.5 |
0.5 |
1.6 |
0.5 |
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1.7 |
ns |
Fall Time |
tf |
0.5 |
1.5 |
0.5 |
1.6 |
0.5 |
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1.7 |
ns |
NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Iinear fpm is maintained. Outputs are terminated through a 50±ohm resistor to ±2.0 volts.
MC10H117
L SUFFIX
CERAMIC PACKAGE
CASE 620±10
P SUFFIX
PLASTIC PACKAGE
CASE 648±08
FN SUFFIX
PLCC
CASE 775±02
LOGIC DIAGRAM
4
5
3
6 2
7
9
10
11 14
15
12
13
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
DIP
PIN ASSIGNMENT
VCC1 |
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1 |
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16 |
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VCC2 |
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AOUT |
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2 |
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15 |
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BOUT |
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AOUT |
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3 |
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14 |
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BOUT |
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A1IN |
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4 |
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13 |
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B1IN |
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A1IN |
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5 |
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12 |
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B1IN |
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A2IN |
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6 |
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11 |
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B2IN |
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A2IN |
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7 |
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10 |
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B2IN |
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VEE |
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8 |
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9 |
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A2IN, B2IN |
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Pin assignment is for Dual±in±Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 6±11 of the Motorola MECL Data Book (DL122/D).
3/93
Motorola, Inc. 1996 |
2±223 |
REV 5 |