July 1990
Revised May 1999
74ACTQ153
Quiet Series Dual 4-Input Multiplexer
General Description
The ACTQ153 is a high-speed dual 4-input multiplexer with common select inputs and individual enable inputs for each section. It can select two lines of data from four sources. The two buffered outputs present data in the true (noninverted) form. In addition to multiplexer operation, the ACTQ153 can act as a function generator and generate any two functions of three variables.
Features
■Outputs source/sink 24 mA
■ACTQ153 has TTL-compatible inputs
■Guaranteed simultaneous switching noise level and dynamic threshold performance
■Guaranteed pin-to-pin skew AC performance
■Improved latch-up immunity
Ordering Code:
Order Number |
Package Number |
Package Description |
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74ACTQ153SC |
M20B |
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide |
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74ACTQ153PC |
N20A |
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide |
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Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols |
Connection Diagram |
IEEE/IEC
Pin Descriptions
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Pin Names |
Description |
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I0a - 13a |
Side A Data Inputs |
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I0b - 13b |
Side B Data Inputs |
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S0, S1 |
Common Select Inputs |
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Side A Enable Input |
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E |
a |
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Side B Enable Input |
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E |
b |
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Za |
Side A Output |
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Zb |
Side B Output |
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FACTä, FACT Quiet Seriesä, and GTOä are trademarks of Fairchild Semiconductor Corporation.
Multiplexer Input-4 Dual Series Quiet 74ACTQ153
© 1999 Fairchild Semiconductor Corporation |
DS010244.prf |
www.fairchildsemi.com |
74ACTQ153
Functional Description
The ACTQ153 is a dual 4-input multiplexer. It can select two bits of data from up to four sources under the control of the common Select inputs (S0, S1). The two 4-input multi-
plexer circuits have individual active-LOW Enables (Ea, Eb) which can be used to strobe the outputs independently. When the Enables (Ea, Eb) are HIGH, the corresponding outputs (Az, Zb) are forced LOW. The ACTQ153 is the logic implementation of a 2-pole, 4-position switch, where the position of the switch is determined by the logic levels supplied to the Select inputs. The logic equations for the outputs are shown below.
Za = Ea • (I0a • S1 • S0 + I1a • S1 • S0 +
I2a • S1 •S0 + I3a • S1 • S0)
Zb = Eb • (I0b • S1 • S0 • I1b • S1 • S0 + I2b • S1 • S0 +I3b • S1 • S0)
Logic Diagram
Truth Table
Select |
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Inputs (a or b) |
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Outputs |
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Inputs |
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S0 |
S1 |
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I0 |
I1 |
I2 |
I3 |
Z |
E |
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X |
X |
H |
X |
X |
X |
X |
L |
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L |
L |
L |
L |
X |
X |
X |
L |
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L |
L |
L |
H |
X |
X |
X |
H |
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H |
L |
L |
X |
L |
X |
X |
L |
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H |
L |
L |
X |
H |
X |
X |
H |
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L |
H |
L |
X |
X |
L |
X |
L |
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L |
H |
L |
X |
X |
H |
X |
H |
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H |
H |
L |
X |
X |
X |
L |
L |
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H |
H |
L |
X |
X |
X |
H |
H |
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H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) |
−0.5V to +7.0V |
DC Input Diode Current (IIK) |
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VI = −0.5V |
−20 mA |
VI = VCC + 0.5V |
+20 mA |
DC Input Voltage (VI) |
−0.5V to VCC + 0.5V |
DC Output Diode Current (IOK) |
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VO = −0.5V |
−20 mA |
VO = VCC + 0.5V |
+20 mA |
DC Output Voltage (VO) |
−0.5V to VCC + 0.5V |
DC Output Source |
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or Sink Current (IO) |
±50 mA |
DC VCC or Ground Current |
±50 mA |
per Output Pin (ICC or IGND) |
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Storage Temperature (TSTG) |
−65°C to +150°C |
DC Latch-Up Source or Sink Current |
±300 mA |
Junction Temperature (TJ) |
140°C |
PDIP |
Recommended Operating
Conditions
Supply Voltage (VCC) |
4.5V to 5.5V |
Input Voltage (VI) |
0V to VCC |
Output Voltage (VO) |
0V to VCC |
Operating Temperature (TA) |
−40°C to +85°C |
Minimum Input Edge Rate V/ |
t |
VIN from 0.8V to 2.0V |
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VCC @ 4.5V, 5.5V |
125 mV/ns |
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACTä circuits outside databook specifications.
DC Electrical Characteristics
Symbol |
Parameter |
VCC |
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TA = +25°C |
TA = −40°C to +85°C |
Units |
Conditions |
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(V) |
Typ |
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Guaranteed Limits |
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VIH |
Minimum HIGH Level |
4.5 |
1.5 |
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2.0 |
2.0 |
V |
VOUT = 0.1V |
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Input Voltage |
5.5 |
1.5 |
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2.0 |
2.0 |
or VCC − 0.1V |
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VIL |
Maximum LOW Level |
4.5 |
1.5 |
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0.8 |
0.8 |
V |
VOUT = 0.1V |
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Input Voltage |
5.5 |
1.5 |
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0.8 |
0.8 |
or VCC − 0.1V |
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VOH |
Minimum HIGH Level |
4.5 |
4.49 |
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4.4 |
4.4 |
V |
IOUT = −50 μA |
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Output Voltage |
5.5 |
5.49 |
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5.4 |
5.4 |
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VIN = VIL or VIH |
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4.5 |
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3.86 |
3.76 |
V |
IOH = −24 mA |
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5.5 |
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4.86 |
4.76 |
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IOH = −24 mA (Note 2) |
VOL |
Maximum LOW Level |
4.5 |
0.001 |
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0.1 |
0.1 |
V |
IOUT = 50 μA |
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Output Voltage |
5.5 |
0.001 |
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0.1 |
0.1 |
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VIN = VIL or VIH |
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4.5 |
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0.36 |
0.44 |
V |
IOL = 24 mA |
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5.5 |
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0.36 |
0.44 |
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IOL = 24 mA (Note 2) |
IIN |
Maximum Input |
5.5 |
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±0.1 |
±1.0 |
μA |
VI = VCC, GND |
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Leakage Current |
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ICCT |
Maximum |
5.5 |
0.6 |
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1.5 |
μA |
VI = VCC − 2.1V |
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ICC/Input |
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IOLD |
Minimum Dynamic |
5.5 |
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75 |
mA |
VOLD = 1.65V Max |
IOHD |
Output Current (Note 3) |
5.5 |
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−75 |
mA |
VOHD = 3.85V Min |
ICC |
Maximum Quiescent |
5.5 |
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8.0 |
80.0 |
μA |
VIN = VCC |
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Supply Current |
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or GND |
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VOLP |
Maximum HIGH Level |
5.0 |
1.1 |
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1.5 |
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V |
Figure 1Figure 2 |
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Output Noise |
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(Note 4)(Note 5) |
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VOLV |
Maximum LOW Level |
5.0 |
−0.6 |
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−1.2 |
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V |
Figure 1Figure 2 |
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Output Noise |
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VIHD |
Minimum HIGH Level |
5.0 |
1.9 |
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2.2 |
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V |
(Note 4)(Note 6) |
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Dynamic Input Voltage |
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VILD |
Maximum LOW Level |
5.0 |
1.2 |
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0.8 |
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V |
(Note 4)(Note 6) |
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Dynamic Input Voltage |
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Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
74ACTQ153
3 |
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