July 1988
Revised September 2000
74ACT843
9-Bit Transparent Latch
General Description
The ACT843 bus interface latch is designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths.
Features
■TTL compatible inputs
■3-STATE outputs for bus interfacing
Ordering Code:
Order Number |
Package Number |
Package Description |
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74ACT843SC |
M24B |
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide |
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74ACT843SPC |
N24C |
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide |
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Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. (SPC not available in Tapeand Reel.)
Logic Symbols |
Connection Diagram |
IEEE/IEC
Pin Descriptions
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Pin Names |
Description |
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D0–D8 |
Data Inputs |
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O0–O8 |
Data Outputs |
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Output Enable |
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OE |
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LE |
Latch Enable |
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Clear |
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CLR |
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Preset |
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PRE |
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FACT is a trademark of Fairchild Semiconductor Corporation
Latch Transparent Bit-9 74ACT843
© 2000 Fairchild Semiconductor Corporation |
DS009800 |
www.fairchildsemi.com |
74ACT843
Functional Description
The ACT843 consists of nine D-type latches with 3-STATE outputs. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. This allows asynchronous operation, as the output transition follows the data in transition. On the LE HIGH-to-LOW transition, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state. In addition to
the LE and OE pins, the ACT843 has a Clear (CLR) pin and a Preset (PRE) pin. These pins are ideal for parity bus interfacing in high performance systems. When CLR is LOW, the outputs are LOW if OE is LOW. When CLR is HIGH, data can be entered into the latch. When PRE is LOW, the outputs are HIGH if OE is LOW. Preset overrides CLR.
Function Tables
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Inputs |
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Internal |
Outputs |
Function |
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CLR |
PRE |
OE |
LE |
D |
Q |
O |
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H |
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H |
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H |
H |
L |
L |
Z |
High Z |
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H |
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H |
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H |
H |
H |
H |
Z |
High Z |
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H |
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H |
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H |
L |
X |
NC |
Z |
Latched |
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H |
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H |
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L |
H |
L |
L |
L |
Transparent |
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H |
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H |
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L |
H |
H |
H |
H |
Transparent |
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H |
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H |
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L |
L |
X |
NC |
NC |
Latched |
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H |
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L |
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L |
X |
X |
H |
H |
Preset |
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L |
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H |
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L |
X |
X |
L |
L |
Clear |
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L |
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L |
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L |
X |
X |
H |
H |
Preset |
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L |
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H |
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H |
L |
X |
L |
Z |
Clear/High Z |
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H |
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L |
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H |
L |
X |
H |
Z |
Preset/High Z |
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H = HIGH Voltage |
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Level |
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L = LOW Voltage Level |
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X = Immaterial |
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Z = High Impedance |
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NC = No Change |
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Logic Diagram
www.fairchildsemi.com |
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