Fairchild Semiconductor 74ACTQ00SCX, 74ACTQ00SC, 74ACTQ00PC, 74ACTQ00MTCX, 74ACTQ00MTC Datasheet
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August 1990
Revised April 1999
74ACTQ00
Quiet Seriesä Quad 2-Input NAND Gate
General Description
The ACTQ00 contains four 2-input NAND gates and utilizes Fairchild FACT Quiet Seriesä technology to guarantee quiet output switching and improve dynamic threshold performance FACT Quiet Series features GTOä output control and undershoot corrector in addition to a split ground bus for superior ACMOS performance.
Features
■ICC reduced by 50%
■Guaranteed simultaneous switching noise level and dynamic threshold performance
■Improved latch-up immunity
■Outputs source/sink 24 mA
■Has TTL-compatible inputs
Ordering Code:
Order Number |
Package Number |
Package Description |
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74ACTQ00SC |
M14A |
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body |
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74ACTQ00PC |
N14A |
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol |
Connection Diagram |
IEEE/IEC |
Pin Assignment for |
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DIP and SOIC |
Pin Descriptions
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Pin Names |
Description |
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An, Bn |
Inputs |
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Outputs |
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O |
n |
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FACTä, Quiet Seriesä, FACT Quiet Seriesä, and GTOä are trademarks of Fairchild Semiconductor Corporation.
Gate NAND Input-2 Quad äSeries Quiet 74ACTQ00
© 1999 Fairchild Semiconductor Corporation |
DS010888.prf |
www.fairchildsemi.com |
74ACTQ00
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) |
−0.5V to +7.0V |
DC Input Diode Current (IIK) |
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VI = −0.5V |
−20 mA |
VI = VCC + 0.5V |
+20 mA |
DC Input Voltage (VI) |
−0.5V to VCC + 0.5V |
DC Output Diode Current (IOK) |
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VO = −0.5V |
−20 mA |
VO = VCC + 0.5V |
+20 mA |
DC Output Voltage (VO) |
−0.5V to VCC + 0.5V |
DC Output Source |
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or Sink Current (IO) |
±50 mA |
DC VCC or Ground Current |
±50 mA |
per Output Pin (ICC or IGND) |
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Storage Temperature (TSTG) |
−65°C to +150°C |
DC Latch-up Source |
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or Sink Current |
±300 mA |
Junction Temperature (TJ) |
140°C |
PDIP |
Recommended Operating
Conditions
Supply Voltage (VCC) |
4.5V to 5.5V |
Input Voltage (VI) |
0V to VCC |
Output Voltage (VO) |
0V to VCC |
Operating Temperature (TA) |
−40°C to +85°C |
Minimum Input Edge Rate ( V/ |
t) |
VIN from 0.8V to 2.0V |
125 mV/ns |
VCC @ 4.5V, 5.5V |
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Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not
DC Electrical Characteristics
Symbol |
Parameter |
VCC |
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TA = +25°C |
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TA = −40°C to +85°C |
Units |
Conditions |
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(V) |
Typ |
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Guaranteed Limits |
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VIH |
Minimum HIGH Level |
4.5 |
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1.5 |
2.0 |
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2.0 |
V |
VOUT = 0.1V |
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Input Voltage |
5.5 |
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1.5 |
2.0 |
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2.0 |
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or VCC − 0.1V |
VIL |
Maximum LOW Level |
4.5 |
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1.5 |
0.8 |
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0.8 |
V |
VOUT = 0.1V |
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Input Voltage |
5.5 |
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1.5 |
0.8 |
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0.8 |
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or VCC − 0.1V |
VOH |
Minimum HIGH Level |
4.5 |
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4.49 |
4.4 |
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4.4 |
V |
IOUT = −50 μA |
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Output Voltage |
5.5 |
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5.49 |
5.4 |
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5.4 |
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VIN = VIL or VIH |
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4.5 |
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3.86 |
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3.76 |
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IOH = −24 mA |
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5.5 |
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4.86 |
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4.76 |
V |
IOH = −24 mA (Note 2) |
VOL |
Maximum LOW Level |
4.5 |
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0.001 |
0.1 |
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0.1 |
V |
IOUT = 50 μA |
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Output Voltage |
5.5 |
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0.001 |
0.1 |
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0.1 |
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VIN = VIL or VIH |
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4.5 |
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0.36 |
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0.44 |
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IOL = 24 mA |
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5.5 |
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0.36 |
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0.44 |
V |
IOL = 24 mA (Note 2) |
IIN |
Maximum Input Leakage Current |
5.5 |
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±0.1 |
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±1.0 |
μA |
VI = VCC, GND |
ICCT |
Maximum ICC/Input |
5.5 |
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0.6 |
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1.5 |
mA |
V I = VCC − 2.1V |
IOLD |
Minimum Dynamic |
5.5 |
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75 |
mA |
VOLD = 1.65V Max |
IOHD |
Output Current (Note 3) |
5.5 |
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−75 |
mA |
VOHD = 3.85V Min |
ICC |
Maximum Quiescent Supply Current |
5.5 |
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2.0 |
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20.0 |
μA |
VIN = VCC or GND |
VOLP |
Quiet Output Maximum Dynamic |
5.0 |
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1.1 |
1.5 |
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V |
Figure 1, Figure 2 |
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VOL |
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(Note 4)(Note 5) |
VOLV |
Quiet Output Minimum Dynamic |
5.0 |
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−0.6 |
−1.2 |
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V |
Figure 1, Figure 2 |
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VOL |
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(Note 4)(Note 5) |
VIHD |
Minimum HIGH Level Dynamic |
5.0 |
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1.9 |
2.2 |
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V |
(Note 4)(Note 6) |
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Input Voltage |
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VILD |
Maximum LOW Level Dynamic |
5.0 |
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1.2 |
0.8 |
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V |
(Note 4)(Note 6) |
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Input Voltage |
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Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: DIP package.
Note 5: Max number of outputs defined as (n). Data inputs are 0V to 3V. One output @ GND.
Note 6: Max number of data inputs (n) switching. (n−1) inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz.
www.fairchildsemi.com |
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