Fairchild Semiconductor 74ACTQ10SCX, 74ACTQ10SC, 74ACTQ10PC, 74ACTQ10MTCX, 74ACTQ10MTC Datasheet

August 1990

Revised August 2000

74ACTQ10

Quiet Series Triple 3-Input NAND Gate

General Description

The ACTQ10 contains three, 3-input NAND gates and utilizes Fairchild FACT Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector in addition to a split ground bus for superior ACMOS performance.

Features

■ICC reduced by 50%

■Guaranteed simultaneous switching noise level and dynamic threshold performance

■Improved latch-up immunity

■Outputs source/sink 24 mA

■ACTQ 10 has TTL-compatible inputs

Ordering Code:

Order Number	Package Number	Package Description
74ACTQ10SC	M14A	14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74ACTQ10MTC	MTC14	14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACTQ10PC	N14A	14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol	Connection Diagram
	IEEE/IEC

Pin Descriptions

		Pin Names	Descriptions
	An, Bn, Cn		Inputs
			Outputs
	O	n

FACT

, Quiet Series

, FACT Quiet Series

, and GTO are trademarks of Fairchild Semiconductor Corporation.

Gate NAND Input-3 Triple Series Quiet 74ACTQ10

© 2000 Fairchild Semiconductor Corporation

DS010892

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74ACTQ10

Absolute Maximum Ratings(Note 1)

Supply Voltage (VCC)		− 0.5V to + 7.0V
DC Input Diode Current (IIK)
VI =	− 0.5V		− 20 mA
VI =	VCC + 0.5V		+ 20 mA
DC Input Voltage (VI)		− 0.5V to VCC + 0.5V
DC Output Diode Current (IOK)
VO =	− 0.5V		− 20 mA
VO =	VCC + 0.5V		+ 20 mA
DC Output Voltage (VO)		− 0.5V to VCC + 0.5V
DC Output Source
or Sink Current (IO)		±	50 mA
DC VCC or Ground Current
per Output Pin (ICC or IGND)		±	50 mA
Storage Temperature (TSTG)		− 65° C to + 150° C
DC Latch-Up Source or Sink Current		±	300 mA
Junction Temperature (TJ)
PDIP			140° C

Recommended Operating

Conditions

Supply Voltage (VCC)	4.5V to 5.5V
Input Voltage (VI)	0V to VCC
Output Voltage (VO)	0V to VCC
Operating Temperature (TA)	− 40° C to + 85° C
Minimum Input Edge Rate (∆ V/∆ t)	125 mV/ns
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V

Note 1: Absolute maximum ratings are values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside of databook specifications.

DC Electrical Characteristics

Symbol	Parameter	VCC	TA = + 25° C		TA = − 40° C to + 85° C	Units		Conditions
		(V)	Typ	Guaranteed Limits
VIH	Minimum HIGH Level	4.5	1.5	2.0	2.0	V	VOUT =		0.1V
	Input Voltage	5.5	1.5	2.0	2.0		or VCC −			0.1V
VIL	Maximum LOW Level	4.5	1.5	0.8	0.8	V	VOUT =		0.1V
	Input Voltage	5.5	1.5	0.8	0.8		or VCC −			0.1V
VOH	Minimum HIGH Level	4.5	4.49	4.4	4.4	V	IOUT =		−	50 µ A
	Output Voltage	5.5	5.49	5.4	5.4
							VIN =	VILor VIH
		4.5		3.86	3.76	V	IOH =	−	24 mA
		5.5		4.86	4.76		IOH =	−	24 mA (Note 2)
VOL	Maximum LOW Level	4.5	0.001	0.1	0.1	V	IOUT =		50 µ A
	Output Voltage	5.5	0.001	0.1	0.1
							VIN =	VILor VIH
		4.5		0.36	0.44	V	IOL =	24 mA
		5.5		0.36	0.44		IOL =	24 mA (Note 2)
IIN	Maximum Input Leakage Current	5.5		± 0.1	± 1.0	µ A	VI =	VCC, GND
ICCT	Maximum ICC/Input	5.5	0.6		1.5	mA	VI =	VCC − 2.1V
IOLD	Minimum Dynamic	5.5			75	mA	VOLD =		1.65V Max
IOHD	Output Current (Note 3)	5.5			− 75	mA	VOHD =			3.85V Min
ICC	Maximum Quiescent Supply Current	5.5		2.0	20.0	µ A	VIN =	VCC or GND
VOLP	Quiet Output	5.0	1.1	1.5		V	Figures 1, 2
	Maximum Dynamic VOL						(Note 4)(Note 5)
VOLV	Quiet Output	5.0	− 0.6	− 1.2		V	Figures 1, 2
	Minimum Dynamic VOL						(Note 4)(Note 5)
VIHD	Minimum HIGH Level Dynamic Input Voltage	5.0	1.9	2.2		V	(Note 4)(Note 6)
VILD	Maximum LOW Level Dynamic Input Voltage	5.0	1.2	0.8		V	(Note 4)(Note 6)

Note 2: All outputs loaded; thresholds on input associated with output under test.

Note 3: Maximum test duration 2.0 ms, one output loaded at a time.

Note 4: DIP Package.

Note 5: Max number of outputs defined as (n). Data inputs are 0V to 3V. One output @ GND.

Note 6: Max number of data inputs (n) switching. (n-1) inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHZ.

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2

AC Electrical Characteristics

		VCC		TA = + 25° C		TA = − 40° C to + 85° C
Symbol	Parameter	(V)		CL = 50 pF		CL =	50 pF	Units
		(Note 7)	Min	Typ	Max	Min	Max
tPLH	Propagation Delay	5.0	2.0	6.0	7.5	2.0	8.5	ns
tPHL	Propagation Delay	5.0	2.0	6.0	7.5	2.0	8.5	ns
tOSHL	Output to Output	5.0		0.5	1.0		1.0	ns
tOSLH	Skew (Note 8)
Note 7: Voltage	Range 5.0 is 5.0V ± 0.5V.

Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.

Capacitance

Symbol	Parameter	Typ	Units		Conditions
CIN	Input Capacitance	4.5	pF	VCC =	OPEN
CPD	Power Dissipation Capacitance	85	pF	VCC =	5.0V

74ACTQ10

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