July 1988
Revised September 2000
74ACT825
8-Bit D-Type Flip-Flop
General Description
The ACT825 is an 8-bit buffered register. They have Clock Enable and Clear features which are ideal for parity bus interfacing in high performance microprogramming systems. Also included are multiple enables that allow multiuse control of the interface. The ACT825 has noninverting outputs.
Features
■Outputs source/sink 24 mA
■Inputs and outputs are on opposite sides
■TTL compatible inputs
Ordering Code:
Order Number |
Package Number |
Package Description |
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74ACT825SC |
M24B |
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide |
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74ACT825MTC |
MTC24 |
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide |
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74ACT825SPC |
N24C |
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide |
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Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols |
Connection Diagram |
IEEE/IEC
Pin Descriptions
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Pin Names |
Description |
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D0–D7 |
Data Inputs |
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O0–O7 |
Data Outputs |
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2, |
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3 |
Output Enables |
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OE |
1, |
OE |
OE |
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Clock Enable |
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EN |
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Clear |
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CLR |
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CP |
Clock Input |
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FACT is a trademark of Fairchild Semiconductor.
Flop-Flip Type-D Bit-8 74ACT825
© 2000 Fairchild Semiconductor Corporation |
DS009895 |
www.fairchildsemi.com |
74ACT825
Functional Description
The ACT825 consists of eight D-type edge-triggered flipflops. These devices have 3-STATE outputs for bus systems, organized in a broadside pinning. In addition to the clock and output enable pins, the buffered clock (CP) and buffered Output Enable (OE) are common to all flip-flops. The flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH CP transition. With OE1, OE2 and OE3 LOW, the contents of the flip-flops are available at the outputs. When one of OE1, OE2 or OE3 is HIGH, the outputs go to the high impedance state.
Operation of the OE input does not affect the state of the flip-flops. The ACT825 has Clear (CLR) and Clock Enable (EN) pins. These pins are ideal for parity bus interfacing in high performance systems.
When CLR is LOW and OE is LOW, the outputs are LOW. When CLR is HIGH, data can be entered into the flip-flops. When EN is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When EN is HIGH, the outputs do not change state, regardless of the data or clock input transitions.
Function Table
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Inputs |
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Internal |
Output |
Function |
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OE |
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CLR |
EN |
CP |
Dn |
Q |
O |
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H |
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X |
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L |
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L |
L |
Z |
High-Z |
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H |
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X |
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L |
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H |
H |
Z |
High-Z |
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H |
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L |
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X |
X |
X |
L |
Z |
Clear |
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L |
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L |
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X |
X |
X |
L |
L |
Clear |
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H |
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H |
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H |
X |
X |
NC |
Z |
Hold |
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L |
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H |
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H |
X |
X |
NC |
NC |
Hold |
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H |
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H |
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L |
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L |
L |
Z |
Load |
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H |
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H |
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L |
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H |
H |
Z |
Load |
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L |
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H |
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L |
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L |
L |
L |
Load |
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L |
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H |
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L |
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H |
H |
H |
Load |
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H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
NC = No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) |
− 0.5V to 7.0V |
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DC Input Diode Current (IIK) |
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VI = |
− 0.5V |
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− 20 mA |
VI = |
VCC + 0.5V |
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+ 20 mA |
DC Input Voltage (VI) |
− 0.5V to VCC + 0.5V |
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DC Output Diode Current (IOK) |
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VO = |
− 0.5V |
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− 20 mA |
VO = |
VCC + 0.5V |
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+ 20 mA |
DC Output Voltage (VO) |
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+ 0.5V |
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DC Output Source or Sink Current |
± |
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(IO) |
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50 mA |
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DC VCC or Ground Current |
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Per Output Pin (ICC or IGND) |
± |
50 mA |
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Storage Temperature (TSTG) |
− 65° C to + 150° C |
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Junction Temperature (TJ) |
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PDIP |
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140° C |
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Recommended Operating
Conditions
Supply Voltage (VCC) |
4.5V to 5.5V |
Input Voltage (VI) |
0V to VCC |
Output Voltage (VO) |
0V to VCC |
Operating Temperature (TA) |
− 40° C to + 85° C |
Minimum Input Edge Rate (∆ V/∆ t) |
125 mV/ns |
VIN from 0.8V to 2.0V |
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VCC @ 4.5V, 5.5V |
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Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics
Symbol |
Parameter |
VCC |
TA = 25° C |
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TA = − 40° C to + 85° C |
Units |
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Conditions |
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(V) |
Typ |
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Guaranteed Limits |
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VIH |
Minimum HIGH Level |
4.5 |
1.5 |
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2.0 |
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2.0 |
V |
VOUT = |
0.1V |
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Input Voltage |
5.5 |
1.5 |
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2.0 |
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2.0 |
or VCC − 0.1V |
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VIL |
Maximum LOW Level |
4.5 |
1.5 |
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0.8 |
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0.8 |
V |
VOUT = |
0.1V |
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Input Voltage |
5.5 |
1.5 |
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0.8 |
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0.8 |
or VCC − 0.1V |
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VOH |
Minimum HIGH Level |
4.5 |
4.49 |
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4.4 |
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4.4 |
V |
IOUT = |
− 50 µ A |
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Output Voltage |
5.5 |
5.49 |
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5.4 |
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5.4 |
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VIN = |
VIL or VIH |
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4.5 |
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3.86 |
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3.76 |
V |
IOH = |
− |
24 mA |
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5.5 |
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4.86 |
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4.76 |
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IOH = |
− 24 mA (Note 2) |
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VOL |
Maximum LOW Level |
4.5 |
0.001 |
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0.1 |
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0.1 |
V |
IOUT = |
50 µ A |
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Output Voltage |
5.5 |
0.001 |
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0.1 |
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0.1 |
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VIN = |
VIL or VIH |
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4.5 |
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0.36 |
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0.44 |
V |
IOL = |
24 mA |
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5.5 |
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0.36 |
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0.44 |
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IOL = |
24 mA (Note 2) |
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IIN |
Maximum Input Leakage Current |
5.5 |
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± |
0.1 |
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± |
1.0 |
µ A |
VI = |
VCC, GND |
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IOZ |
Maximum |
5.5 |
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± 0.5 |
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± |
5.0 |
µ A |
VI = |
VIL, VIH |
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3-STATE Current |
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VO = |
VCC, GND |
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ICCT |
Maximum ICC/Input |
5.5 |
0.6 |
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1.5 |
mA |
VI = |
VCC − 2.1V |
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IOLD |
Minimum Dynamic |
5.5 |
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75 |
mA |
VOLD = |
1.65V Max |
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IOHD |
Output Current (Note 3) |
5.5 |
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− 75 |
mA |
VOHD = |
3.85V Min |
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ICC |
Maximum Quiescent |
5.5 |
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8.0 |
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80 |
µ A |
VIN = |
VCC or GND |
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Supply Current |
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Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
74ACT825
3 |
www.fairchildsemi.com |
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