November 1988
Revised September 2000
74ACT841
10-Bit Transparent Latch with 3-STATE Outputs
General Description |
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Features |
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The ACT841 bus interface latch is designed to eliminate |
■ ACT841 has TTL-compatible inputs |
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the extra packages required to buffer existing latches and |
■ Outputs source/sink 24 mA |
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provide extra data width for wider address/data paths or |
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■ Non-inverting 3-STATE outputs |
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buses carrying parity. The ACT841 is a 10-bit transparent |
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latch, a 10-bit version of the ACT373. |
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Ordering Code: |
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Order Number |
Package Number |
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Package Description |
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74ACT841SC |
M24B |
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide |
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74ACT841MTC |
MTC24 |
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide |
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74ACT841SPC |
N24C |
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide |
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Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. (SPC not available in Tapeand Reel.)
Logic Symbols |
Connection Diagram |
IEEE/IEC
Pin Descriptions
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Pin Names |
Description |
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D0–D9 |
Data Inputs |
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O0–O9 |
3-STATE Outputs |
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Output Enable |
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OE |
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LE |
Latch Enable |
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FACT is a trademark of Fairchild Semiconductor Corporation.
Outputs STATE-3 with Latch Transparent Bit-10 74ACT841
© 2000 Fairchild Semiconductor Corporation |
DS010156 |
www.fairchildsemi.com |
74ACT841
Functional Description
The ACT841 consists of ten D-type latches with 3-STATE |
On the LE HIGH-to-LOW transition, the data that meets the |
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outputs. The flip-flops appear transparent to the data when |
setup and hold time is latched. Data appears on the bus |
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Latch Enable (LE) is HIGH. This allows asynchronous |
when the Output Enable (OE) is LOW. When |
OE |
is HIGH |
operation, as the output transition follows the data in transi- |
the bus output is in the high impedance state. |
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tion.
Function Table
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Inputs |
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Internal |
Output |
Function |
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OE |
LE |
D |
Q |
O |
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X |
X |
X |
X |
Z |
High Z |
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H |
H |
L |
L |
Z |
High Z |
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H |
H |
H |
H |
Z |
High Z |
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H |
L |
X |
NC |
Z |
Latched |
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L |
H |
L |
L |
L |
Transparent |
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L |
H |
H |
H |
H |
Transparent |
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L |
L |
X |
NC |
NC |
Latched |
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H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
NC = No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com |
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Absolute Maximum Ratings(Note 1)
Supply Voltage (V ) |
− 0.5V to + 7.0V |
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CC |
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DC Input Diode Current (IIK) |
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VI = |
− 0.5V |
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VI = |
VCC + 0.5V |
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DC Input Voltage (VI) |
− |
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DC Output Diode Current (IOK) |
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VO = |
− 0.5V |
− 20 mA |
VO = |
VCC + 0.5V |
+ 20 mA |
DC Output Voltage (VO) |
− 0.5V to VCC + 0.5V |
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DC Output Source |
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or Sink Current (IO) |
± 50 mA |
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DC VCC or Ground Current |
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per Output Pin (ICC or IGND) |
± 50 mA |
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Storage Temperature (TSTG) |
− 65° C to + 150° C |
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Junction Temperature (TJ)
PDIP
Recommended Operating
Conditions
4.5V to 5.5V
0V to VCC
0V to VCC − 40° C to + 85° C
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics
Symbol |
Parameter |
VCC |
TA = + 25° C |
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TA = − 40° C to + 85° C |
Units |
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Conditions |
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(V) |
Typ |
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Guaranteed Limits |
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VIH |
Minimum HIGH Level |
4.5 |
1.5 |
2.0 |
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2.0 |
V |
VOUT = |
0.1V |
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Input Voltage |
5.5 |
1.5 |
2.0 |
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2.0 |
or VCC − |
0.1V |
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VIL |
Maximum LOW Level |
4.5 |
1.5 |
0.8 |
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0.8 |
V |
VOUT = |
0.1V |
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Input Voltage |
5.5 |
1.5 |
0.8 |
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0.8 |
or VCC − |
0.1V |
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VOH |
Minimum HIGH Level |
4.5 |
4.49 |
4.4 |
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4.4 |
V |
IOUT = |
− |
50 µ A |
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Output Voltage |
5.5 |
5.49 |
5.4 |
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5.4 |
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VIN = |
VIL or VIH |
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4.5 |
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3.86 |
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3.76 |
V |
IOH = |
− |
24 mA |
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5.5 |
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4.86 |
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4.76 |
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IOH = |
− 24 mA (Note 2) |
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VOL |
Maximum LOW Level |
4.5 |
0.001 |
0.1 |
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0.1 |
V |
IOUT = |
50 µ A |
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Output Voltage |
5.5 |
0.001 |
0.1 |
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0.1 |
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VIN = |
VIL or VIH |
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4.5 |
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0.36 |
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0.44 |
V |
IOL = |
24 mA |
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5.5 |
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0.36 |
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0.44 |
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IOL = |
24 mA (Note 2) |
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IIN |
Maximum Input |
5.5 |
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± |
0.1 |
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± 1.0 |
µ A |
VI = |
VCC, GND |
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Leakage Current |
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IOZ |
Maximum 3-STATE |
5.5 |
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± |
0.5 |
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± 5.0 |
µ A |
VI = |
VIL, VIH |
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Leakage Current |
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VO = |
VCC, GND |
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ICCT |
Maximum |
5.5 |
0.6 |
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1.5 |
µ A |
VI = |
VCC − 2.1V |
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ICC/Input |
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IOLD |
Minimum Dynamic |
5.5 |
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75 |
mA |
VOLD = |
1.65V Max |
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IOHD |
Output Current (Note 3) |
5.5 |
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− 75 |
mA |
VOHD = |
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3.85V Min |
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ICC |
Maximum Quiescent |
5.5 |
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8.0 |
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80.0 |
µ A |
VIN = |
VCC |
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Supply Current |
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or GND |
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Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
74ACT841
3 |
www.fairchildsemi.com |
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