Fairchild Semiconductor 74ACT823SPC, 74ACT823SCX, 74ACT823SC, 74ACT823MTCX, 74ACT823MTC Datasheet

© 2000 Fairchild Semiconductor Corporation DS009894 www.fairchildsemi.com

July 1988
Revised September 2000

74ACT823 9-Bit D-Type Flip-Flop

74ACT823
9-Bit D-Type Flip-Flop

General Description

The ACT823 is a 9-bit b uffered register. It features Clock
Enable and Clear which are ideal for parity bus interfacing
in high performance microprogramming systems. The
ACT823 offers noninverting outputs.

Features

■ Outputs source/sink 24 mA
■ 3-STATE outputs for bus interfacing
■ Inputs and outputs are on opposite sides
■ TTL compatible inputs

Ordering Code:

Device also available in Tape and Reel. Specify by appending s uffix let te r “X” to the ordering code. (SPC not available in Tape and Reel.)

Logic Symbols

IEEE/IEC

Connection Diagram

Pin Descriptions

FACT is a trademark of Fairchild Semiconductor Corporation.

Order Number Package Number Package Description

74ACT823SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACT823MTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT823SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Pin Names Description

D

0–D8

Data Inputs

O

0–O8

Data Outputs

OE

Output Enable

CLR

Clear
CP Clock Input
EN

Clock Enable

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74ACT823

Functional Description

The ACT823 cons ists of nine D-type edge-triggered f lip­flops. These have 3-STATE outputs for bus systems orga­nized with inputs and out puts on opposit e sides. The buff­ered clock (CP) and buffered Output Enable (OE

) are
common to all flip-flops. The flip-flops will store the state of
their individual D-type inp uts that meet the setup and hold
time requirements on the LOW-to-HIGH CP transition. With
OE

LOW, the contents of the flip-flops are available at the

outputs. When OE

is HIGH, the outputs go to the high

impedance state. Operation of the OE

input does not affect

the state of the flip-flop s. In addi tion to the Cl ock and Out-

put Enable pins, there ar e Clear (CLR

) and Clock Enable

(EN

) pins. These devices are ideal for parity bus interfacing

in high performance systems.
When CLR

is LOW and OE is LOW, the outputs are LO W.

When CLR

is HIGH, data can be entered into the flip-f lops.

When EN

is LOW, data on the inputs is transferred to the
outputs on the LOW-to-HIGH clock transition. When the
EN

is HIGH, the outputs do not change state, regardless of

the data or clock input transitions.

Function Table

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance



= LOW-to-HIGH Transition

NC = No Change

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation d elays.

Inputs Internal Output

Function

OE

CLR EN CP D Q O

HXL



L L Z High Z

HXL



H H Z High Z
H L X X X L Z Clear
L L X X X L L Clear
HHHXX NC Z Hold
LHHXX NC NCHold
HHL



LL ZLoad
HHL



HH ZLoad
LHL



LL LLoad
LHL



HH HLoad

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74ACT823

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute max imum ratings are those values beyond which damage

to the device may occu r. The databook spe cificatio ns shou ld be met, wit h­out exception, to ensure that the system de sign is relia ble over its p ower
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.

DC Electrical Characteristics

Note 2: All outputs loaded; thres holds on input associate d w it h output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.

Supply Voltage (VCC) −0.5V to 7.0V
DC Input Diode Current (I

IK

)

V

I

= −0.5V −20 mA

V

I

= VCC + 0.5V +20 mA

DC Input Voltage (V

I

) −0.5V to VCC + 0.5V

DC Output Diode Current (I

OK

)

V

O

= −0.5V −20 mA

V

O

= VCC + 0.5V +20 mA

DC Output Voltage (V

O

) −0.5V to VCC + 0.5V

DC Output Source or Sink Current

(I

O

) ±50 mA

DC V

CC

or Ground Current

per Output Pin (I

CC

or I

GND

) ±50 mA

Storage Temperature (T

STG

) −65°C to +150°C

Junction Temperature (T

J

)

PDIP 140

°C

Supply Voltage (V

CC

) 4.5V to 5.5V

Input Voltage (V

I

)0V to V

CC

Output Voltage (VO)0V to V

CC

Operating Temperature (TA) −40°C to +85°C
Minimum Input Edge Rate (

∆V/∆t) 125 mV/ns

V

IN

from 0.8V to 2.0V

V

CC

@ 4.5V, 5.5V

Symbol Parameter

V

CC

TA = 25°CT

A

= −40°C to +85°C

Units Conditions

(V) Typ Guaranteed Limits

V

IH

Minimum HIGH Level 4.5 1.5 2.0 2.0

V

V

OUT

= 0.1V

Input Voltage 5.5 1.5 2.0 2.0 or VCC −0.1V

V

IL

Maximum LOW Level 4.5 1.5 0.8 0.8

V

V

OUT

= 0.1V

Input Voltage 4.5 1.5 0.8 0.8 or V

CC

−0.1V

V

OH

Minimum HIGH Level 4.5 4.49 4.4 4.4

VI

OUT

= −50 µA

5.49 5.4 5.4
VIN = VIL or V

IH

4.5 3.86 3.76 V IOH = −24 mA

4.86 4.76 I

OH

= −24 mA (Note 2)

V

OL

Maximum LOW Level 4.5 0.001 0.1 0.1

VI

OUT

= 50 µA

Output Voltage 5.5 0.001 0.1 0.1

VIN = VIL or V

IH

4.5 0.36 0.44 V IOL = 24 mA

5.5 0.36 0.44 IOL = 24 mA (Note 2)

I

IN

Maximum Input

5.5 ±0.1 ±1.0 µAVI = VCC, GND

Leakage Current

I

OZ

Maximum 3- STATE

5.5 ±0.5 ±5.0 µA

VI = VIL, V

IH

Current VO = VCC, GND

I

CCT

Maximum ICC/Input 5.5 0.6 1.5 mA VI = VCC −2.1V

I

OLD

Minimum Dynamic 5.5 75 mA V

OLD

= 1.65V Max

I

OHD

Output Current (Note 3) 5.5 −75 mA V

OHD

= 3.85V Min

I

CC

Maximum Quiescent

5.5 8.0 80 µA

VIN = V

CC

Supply Current or GND