March 1994
Revised November 1999
74ABT16373
16-Bit Transparent D-Type Latch with 3-STATE Outputs
General Description
The ABT16373 contains sixteen non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear transparent to the data when the Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in high Z state.
Features
■Separate control logic for each byte
■16-bit version of the ABT373
■High impedance glitch free bus loading during entire power up and power down cycle
■Non-destructive hot insertion capability
■Guaranteed latch-up protection
Ordering Code:
Order Number |
Package Number |
Package Description |
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74ABT16373CSSC |
MS48A |
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide |
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74ABT16373CMTD |
MTD48 |
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide |
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Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol |
Connection Diagram |
Pin Descriptions
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Pin Names |
Description |
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n |
Output Enable Input (Active LOW) |
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OE |
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LEn |
Latch Enable Input |
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D0–D15 |
Data Inputs |
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O0–O15 |
Outputs |
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Outputs STATE-3 with Latch Type-D Transparent Bit-16 74ABT16373
© 1999 Fairchild Semiconductor Corporation |
DS011666 |
www.fairchildsemi.com |
74ABT16373
Functional Description
The ABT16373 contains sixteen D-type latches with 3- STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable (LEn) input is HIGH, data on the Dn enters the latches. In this condition the latches are transparent, i.e., a latch output will change states each time its D input changes. When LEn is LOW, the latches store information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LEn. The 3- STATE standard outputs are controlled by the Output Enable (OEn) input. When OEn is LOW, the standard out-
puts are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.
Logic Diagrams
Truth Tables
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Inputs |
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Outputs |
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LE1 |
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OE1 |
D0–D7 |
O0–O7 |
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X |
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H |
X |
Z |
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H |
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L |
L |
L |
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H |
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L |
H |
H |
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L |
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L |
X |
(Previous) |
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Inputs |
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Outputs |
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LE2 |
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OE2 |
D8–D15 |
O8–O15 |
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X |
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H |
X |
Z |
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H |
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L |
L |
L |
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H |
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L |
H |
H |
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L |
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L |
X |
(Previous) |
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H = HIGH Voltage Level |
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L = LOW Voltage Level |
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X = Immaterial |
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Z = High Impedance |
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Previous = |
previous output prior to HIGH-to-LOW transition of LE |
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www.fairchildsemi.com |
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