October 1989
Revised August 2000
100343
Low Power 8-Bit Latch
General Description
The 100343 contains eight D-type latches, individual inputs, (Dn), outputs (Qn), a common enable pin (E), and a
latch enable pin (LE). A Q output follows its D input when both E and LE are LOW. When either E or LE (or both) are HIGH, a latch stores the last valid data present on its D input prior to E or LE going HIGH.
The 100343 outputs are designed to drive a 50Ω termination resistor to − 2.0V. All inputs have 50 kΩ pull-down resistors.
Features
■Low power operation
■2000V ESD protection
■Voltage compensated operating range = − 4.2V to − 5.7V
■Available to industrial grade temperature range
Ordering Code:
Order Number |
Package Number |
Package Description |
|
|
|
100343PC |
N24E |
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide |
|
|
|
100343QC |
V28A |
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square |
|
|
|
100343QI |
V28A |
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square |
|
|
Industrial Temperature Range (− 40° C to + 85° C) |
|
|
|
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol |
Connection Diagrams |
|
24-Pin DIP |
|
|
|
|
|
|
28-Pin PLCC |
Pin Descriptions |
||||||
|
|
|
|
|
||
|
|
Pin Names |
Description |
|
||
|
|
|
|
|
||
|
|
D0–D7 |
Data Inputs |
|
||
|
|
|
|
Enable Input |
|
|
|
|
E |
|
|
|
|
|
|
|
Latch Enable Input |
|
||
|
|
LE |
|
|
||
|
|
Q0–Q7 |
Data Inputs |
|
||
|
|
NC |
No Connect |
|
||
|
|
|
|
|
|
|
Latch Bit-8 Power Low 100343
© 2000 Fairchild Semiconductor Corporation |
DS010250 |
www.fairchildsemi.com |
100343
Truth Table
|
Inputs |
|
Outputs |
||
Dn |
|
|
|
|
|
|
E |
LE |
Qn |
||
L |
|
L |
L |
L |
|
H |
|
L |
L |
H |
|
X |
H |
X |
Latched (Note 1) |
||
X |
|
X |
H |
Latched (Note 1) |
|
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Note 1: Retains data present before either LE or E went HIGH
Logic Diagram
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 2)
Storage Temperature (TSTG) |
− 65° C to + 150° C |
Maximum Junction Temperature (TJ) |
+ 150° C |
VEE Pin Potential to Ground Pin |
− 7.0V to + 0.5V |
Input Voltage (DC) |
VEE to + 0.5V |
Output Current (DC Output HIGH) |
− 50 mA |
ESD (Note 3) |
≥ 2000V |
Recommended Operating
Conditions
Case Temperature (TC) |
|
Commercial |
0° C to + 85° C |
Industrial |
− 40° C to + 85° C |
Supply Voltage (VEE) |
− 5.7V to − 4.2V |
Note 2: The “Absolute Maximum Ratings” re those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation.
Note 3: ESD testing conforms to MIL-STD-883, Method 3015.
Commercial Version
DC Electrical Characteristics (Note 4)
VEE = − 4.2V to − 5.7V, VCC = VCCA = |
GND, TC = 0° C to + 85° C |
|
|
|
|
|
|||
Symbol |
Parameter |
|
Min |
Typ |
Max |
Units |
|
Conditions |
|
|
|
|
|
|
|
|
|
|
|
VOH |
Output HIGH Voltage |
|
− 1025 |
− 955 |
− 870 |
mV |
VIN = |
VIH (Max) |
Loading with |
VOL |
Output LOW Voltage |
|
− 1830 |
− 1705 |
− 1620 |
mV |
or VIL (Min) |
50Ω to − 2.0V |
|
VOHC |
Output HIGH Voltage |
|
− 1035 |
|
|
mV |
VIN = |
VIH (Min) |
Loading with |
VOLC |
Output LOW Voltage |
|
|
|
− 1610 |
mV |
or VIL (Max) |
50Ω to − 2.0V |
|
VIH |
Input HIGH Voltage |
|
− 1165 |
|
− 870 |
mV |
Guaranteed HIGH Signal for All Inputs |
||
VIL |
Input LOW Voltage |
|
− 1830 |
|
− 1475 |
mV |
Guaranteed LOW Signal for All Inputs |
||
IIL |
Input LOW Current |
|
0.50 |
|
|
µ A |
VIN = |
VIL (Min) |
|
IIH |
Input HIGH Current |
|
|
|
240 |
µ A |
VIN = |
VIH (Max) |
|
IEE |
Power Supply Current |
|
|
|
|
|
Inputs Open |
|
|
|
|
|
− 95 |
|
− 55 |
mA |
VEE = |
− 4.2V to − 4.8V |
|
|
|
|
− 97 |
|
− 55 |
|
VEE = |
− 4.2V to − 5.7V |
|
Note 4: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions.
AC Electrical Characteristics
VEE = − |
4.2V to − 5.7V, VCC = |
VCCA = GND |
|
|
|
|
|
|
|
|
||||||||||
Symbol |
|
|
|
|
|
Parameter |
|
TC = 0° C |
TC = + 25° C |
TC = + 85° C |
Units |
Conditions |
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
Min |
Max |
Min |
Max |
Min |
Max |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
tPLH |
|
|
Propagation Delay |
|
|
|
|
|
|
0.80 |
2.00 |
0.80 |
2.00 |
0.80 |
2.20 |
ns |
Figures 1, 2, 3 |
|||
tPHL |
|
|
Dn to Output |
|
|
|
|
|
|
(Note 5) |
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||
tPLH |
|
|
Propagation Delay |
|
|
|
|
|
|
1.40 |
2.90 |
1.40 |
2.90 |
1.60 |
3.10 |
ns |
Figures 1, 2, 3 |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||
tPHL |
|
|
LE, E to Output |
|
|
|
|
|
|
(Note 5) |
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||
tTLH |
|
|
Transition Time |
|
|
|
|
|
|
0.45 |
2.00 |
0.45 |
2.00 |
0.45 |
2.00 |
ns |
Figures 1, 3 |
|||
tTHL |
|
|
20% to 80%, 80% to 20% |
|
||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
||||||||||
tS |
|
|
Setup Time |
|
D0–D7 |
|
1.0 |
|
1.0 |
|
1.1 |
|
ns |
Figures 1, 4 |
||||||
tH |
|
|
Hold Time |
|
D0–D7 |
|
0.1 |
|
0.1 |
|
0.1 |
|
ns |
Figures 1, 4 |
||||||
tPW(H) |
|
|
Pulse Width HIGH |
|
|
|
|
|
|
2.00 |
|
2.00 |
|
2.00 |
|
ns |
Figures 1, 4 |
|||
|
|
|
LE, |
|
E |
|
|
|
|
|
||||||||||
Note 5: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching.
100343
3 |
www.fairchildsemi.com |
Loading...