Fairchild Semiconductor 100351SCX, 100351SC, 100351QIX, 100351QI, 100351QCX Datasheet

July 1988

Revised August 2000

100351

Low Power Hex D-Type Flip-Flop

General Description

The 100351 contains six D-type edge-triggered, master/ slave flip-flops with true and complement outputs, a pair of common Clock inputs (CPa and CPb) and common Master Reset (MR) input. Data enters a master when both CPa and CPb are LOW and transfers to the slave when CPa and CPb (or both) go HIGH. The MR input overrides all other inputs and makes the Q outputs LOW. All inputs have 50 kΩ pull-down resistors.

Features

■40% power reduction of the 100151

■2000V ESD protection

■Pin/function compatible with 100151

■Voltage compensated operating range:

− 4.2V to − 5.7V

■Available to industrial grade temperature range

Ordering Code:

Order Number	Package Number	Package Description
100351SC	M24B	24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
100351PC	N24E	24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100351QC	V28A	28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100351QI	V28A	28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
		Industrial Temperature Range (− 40° C to + 85° C)

Devises also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol	Connection Diagrams
	24-Pin DIP/SOIC

Pin Descriptions						28-Pin PLCC
		Pin Names			Description
	D0–D5				Data Inputs
	CPa, CPb				Common Clock Inputs
	MR				Asynchronous Master Reset Input
	Q0–Q5				Data Outputs
	Q	0–Q		5	Complementary Data Outputs

Flop-Flip Type-D Hex Power Low 100351

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DS009885

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100351

Truth Tables

(Each Flip-flop)

Synchronous Operation

		Inputs			Outputs
Dn	CPa		CPb	MR	Qn(t+ 1)
L			L	L	L
H			L	L	H
L	L			L	L
H	L			L	H
X	H			L	Qn(t)
X			H	L	Qn(t)
X	L		L	L	Qn(t)

H =	HIGH Voltage Level
L =	LOW Voltage Level
X =	Don’t Care
t =	Time before CP positive transition
t+ 1 =	Time after CP positive transition
=	LOW-to-HIGH transition

Logic Diagram

Asynchronous Operation

		Inputs			Outputs
Dn	CPa		CPb	MR	Qn(t+ 1)
X	X		X	H	L

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Absolute Maximum Ratings(Note 1)

Storage Temperature (TSTG)	− 65° C to + 150° C
Maximum Junction Temperature (TJ)	+ 150° C
VEE Pin Potential to Ground Pin	− 7.0V to + 0.5V
Input Voltage (DC)	VEE to + 0.5V
Output Current (DC Output HIGH)	− 50 mA
ESD (Note 2)	≥ 2000V

Recommended Operating

Conditions

Case Temperature (TC)
Commercial	0° C to + 85° C
Industrial	− 40° C to + 85° C
Supply Voltage (VEE)	− 5.7V to − 4.2V

Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Note 2: ESD testing conforms to MIL-STD-883, Method 3015.

Commercial Version

DC Electrical Characteristics (Note 3)

VEE = − 4.2V to − 5.7V, VCC = VCCA =		GND, TC = 0° C to + 85° C
Symbol	Parameter		Min	Typ	Max	Units			Conditions
VOH	Output HIGH Voltage		− 1025	− 955	− 870	mV	VIN = VIH (Max)			Loading with
VOL	Output LOW Voltage		− 1830	− 1705	− 1620		or VIL (Min)			50Ω to −	2.0V
VOHC	Output HIGH Voltage		− 1035			mV	VIN =	VIH (Min)		Loading with
VOLC	Output LOW Voltage				− 1610		or VIL (Max)			50Ω to −	2.0V
VIH	Input HIGH Voltage		− 1165		− 870	mV	Guaranteed HIGH Signal for All Inputs
VIL	Input LOW Voltage		− 1830		− 1475	mV	Guaranteed LOW Signal for All Inputs
IIL	Input LOW Current		0.50			µ A	VIN =	VIL (Min)
IIH	Input HIGH Current
		MR			350
		D0–D5			240	µ A	VIN =	VIH (Max)
	CPa, CPb				350
IEE	Power Supply Current		− 129		− 62	mA	Inputs OPEN

Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions.

DIP AC Electrical Characteristics

VEE = − 4.2V to − 5.7V, VCC = VCCA =		GND
Symbol	Parameter		TC = 0° C		TC = + 25° C		TC = + 85° C		Units	Conditions
			Min	Max	Min	Max	Min	Max
fMAX	Toggle Frequency		375		375		375		MHz	Figures 2, 3
tPLH	Propagation Delay		0.80	2.00	0.80	2.0	0.90	2.10	ns	Figures 1, 3
tPHL	CPa, CPb to Output
tPLH	Propagation Delay		1.10	2.30	1.10	2.30	1.20	2.40	ns	Figures 1, 4
tPHL	MR to Output
tTLH	Transition Time		0.35	1.20	0.35	1.20	0.35	1.20	ns	Figures 1, 3
tTHL	20% to 80%, 80% to 20%
tS	Setup Time
	D0–D5		0.40		0.40		0.40		ns	Figure 5
	MR (Release Time)		1.60		1.60		1.60			Figure 4
tH	Hold Time		0.80		0.80		0.80		ns	Figure 5
	D0–D5
tPW(H)	Pulse Width HIGH		2.00		2.00		2.00		ns	Figures 3, 4
	CPa, CPb, MR

100351

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