Fairchild Semiconductor 74ABT573CSJX, 74ABT573CSJ, 74ABT573CSCX, 74ABT573CSC, 74ABT573CPC Datasheet

January 1993

Revised November 1999

74ABT573

Octal D-Type Latch with 3-STATE Outputs

General Description

The ABT573 is an octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs.

This device is functionally identical to the ABT373 but has broadside pinouts.

Features

■Inputs and outputs on opposite sides of package allow easy interface with microprocessors

■Useful as input or output port for microprocessors

■Functionally identical to ABT373

■3-STATE outputs for bus interfacing

■Output sink capability of 64 mA, source capability of 32 mA

■Guaranteed output skew

■Guaranteed multiple output switching specifications

■Output switching specified for both 50 pF and 250 pF loads

■Guaranteed simultaneous switching, noise level and dynamic threshold performance

■Guaranteed latchup protection

■High impedance glitch-free bus loading during entire power up and power down

■Nondestructive hot insertion capability

Ordering Code:

Order Number	Package Number	Package Description
74ABT573CSC	M20B	20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ABT573CSJ	M20D	20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT573CMSA	MSA20	20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT573CMTC	MTC20	20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ABT573CPC	N20A	20-Lead Plastic Dual-In-Line (PDIP), JEDEC MS-01, 0.300” Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram	Pin Descriptions
	Pin Names			Descriptions
		D0–D7		Data Inputs
		LE		Latch Enable Input (Active HIGH)
				3-STATE Output Enable Input (Active LOW)
		OE
		O0–O7		3-STATE Latch Outputs

Outputs STATE-3 with Latch Type-D Octal 74ABT573

© 1999 Fairchild Semiconductor Corporation

DS011548

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74ABT573

Functional Description

The ABT573 contains eight D-type latches with 3-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches.

Logic Diagram

Function Table

				Inputs			Outputs
			OE		LE	D	O
			L		H	H	H
			L		H	L	L
			L		L	X	O0
			H		X	X	Z
H = HIGH Voltage Level
L =		LOW Voltage Level
X =		Immaterial
O0 = Value stored from previous clock cycle

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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Absolute Maximum Ratings(Note 1)

Storage Temperature	− 65° C to + 150° C
Ambient Temperature under Bias	− 55° C to + 125° C
Junction Temperature under Bias	− 55° C to + 150° C
VCC Pin Potential to Ground Pin	− 0.5V to + 7.0V
Input Voltage (Note 2)	− 0.5V to + 7.0V
Input Current (Note 2)	− 30 mA to + 5.0 mA
Voltage Applied to Any Output
in the Disabled or
Power-Off State	− 0.5V to + 5.5V
in the HIGH State	− 0.5V to VCC
Current Applied to Output
in LOW State (Max)	Twice the rated IOL (mA)
DC Latchup Source Current	− 500 mA
Over Voltage Latchup (I/O)	10V

Recommended Operating

Conditions

Free Air Ambient Temperature	− 40° C to + 85° C
Supply Voltage	+ 4.5V to + 5.5V
Minimum Input Edge Rate (∆ V/∆ t)
Data Input	50 mV/ns
Enable Input	20 mV/ns

Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.

Note 2: Either voltage limit or current limit is sufficient to protect inputs.

DC Electrical Characteristics

Symbol

Parameter

Min

Typ

Max

Units

VCC

Conditions

VIH

Input HIGH Voltage

2.0

V

Recognized HIGH Signal

VIL

Input LOW Voltage

0.8

V

Recognized LOW Signal

VCD

Input Clamp Diode Voltage

− 1.2

V

Min

IIN =

− 18 mA

VOH

Output HIGH Voltage

2.5

V

Min

IOH =

−

3 mA

2.0

IOH =

−

32 mA

VOL

Output LOW Voltage

0.55

V

Min

IOL =

64 mA

IIH

Input HIGH Current

1

µ A

Max

VIN =

2.7V (Note 4)

1

VIN =

VCC

IBVI

Input HIGH Current

7

µ A

Max

VIN =

7.0V

Breakdown Test

IIL

Input LOW Current

− 1

µ A

Max

VIN =

0.5V (Note 4)

− 1

VIN =

0.0V

VID

Input Leakage Test

4.75

V

0.0

IID =

1.9 µ A

All Other Pins Grounded

IOZH

Output Leakage Current

10

µ A

0 −

5.5V

VOUT =

2.7V;

=

2.0V

OE

IOZL

Output Leakage Current

− 10

µ A

0 −

5.5V

VOUT =

0.5V;

=

2.0V

OE

IOS

Output Short-Circuit Current

− 100

− 275

mA

Max

VOUT =

0.0V

ICEX

Output HIGH Leakage Current

50

µ A

Max

VOUT =

VCC

IZZ

Bus Drainage Test

100

µ A

0.0

VOUT =

5.5V; All Others GND

ICCH

Power Supply Current

50

µ A

Max

All Outputs HIGH

ICCL

Power Supply Current

30

mA

Max

All Outputs LOW

ICCZ

Power Supply Current

50

µ A

Max

=

OE

VCC

All Others at VCC or GND

ICCT

Additional ICC/Input

Outputs Enabled

2.5

mA

VI =

VCC − 2.1V

Outputs 3-STATE

2.5

mA

Max

Enable Input VI = VCC − 2.1V

Outputs 3-STATE

2.5

mA

Data Input VI = VCC − 2.1V

All Others at VCC or GND

ICCD

Dynamic ICC

No Load

mA/

Max

Outputs Open

(Note 4)

0.12

MHz

=

GND, LE = VCC (Note 3)

OE

One Bit Toggling, 50% Duty Cycle

Note 3: For

8 bits toggling, ICCD <

0.8 mA/MHz.

Note 4: Guaranteed but not tested.

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74ABT573

DC Electrical Characteristics

	Symbol	Parameter	Min	Typ	Max	Units	VCC		Conditions
								CL = 50 pF, RL = 500Ω
	VOLP	Quiet Output Maximum Dynamic VOL		0.7	1.0	V	5.0	TA =	25° C (Note 5)
	VOLV	Quiet Output Minimum Dynamic VOL	− 1.5	− 1.2		V	5.0	TA =	25° C (Note 5)
	VOHV	Minimum HIGH Level Dynamic Output Voltage	2.5	3.0		V	5.0	TA =	25° C (Note 6)
	VIHD	Minimum HIGH Level Dynamic Input Voltage	2.2	1.8		V	5.0	TA =	25° C (Note 7)
	VILD	Maximum LOW Level Dynamic Input Voltage		1.0	0.7	V	5.0	TA =	25° C (Note 7)

Note 5: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.

Note 6: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.

Note 7: Max number of data inputs (n) switching. n − 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD). Guaranteed, but not tested.

AC Electrical Characteristics

(SOIC and SSOP Package)
			TA = + 25° C			TA = − 40° C to + 85° C
Symbol	Parameter		VCC =	+ 5.0V		VCC =	4.5V to 5.5V		Units
			CL =	50 pF		CL =		50 pF
		Min	Typ		Max	Min		Max
tPLH	Propagation Delay	1.9	2.7		4.5	1.9		4.5	ns
tPHL	Dn to On	1.9	2.8		4.5	1.9		4.5
tPLH	Propagation Delay	2.0	3.1		5.0	2.0		5.0	ns
tPHL	LE to On	2.0	3.0		5.0	2.0		5.0
tPZH	Output Enable Time	1.5	3.1		5.3	1.5		5.3	ns
tPZL		1.5	3.1		5.3	1.5		5.3
tPHZ	Output Disable Time	2.0	3.6		5.4	2.0		5.4	ns
tPLZ	Time	2.0	3.4		5.4	2.0		5.4

AC Operating Requirements

(SOIC and SSOP Package)
			TA = + 25° C			TA = − 40° C to + 85° C
Symbol	Parameter		VCC =	+ 5.0V		VCC =	4.5V to 5.5V		Units
			CL =	50 pF		CL =		50 pF
		Min	Typ		Max	Min		Max
fTOGGLE	Max Toggle Frequency		100						MHz
tS(H)	Set Time, HIGH	1.5				1.5			ns
tS(L)	or LOW Dn to LE	1.5				1.5
tH(H)	Hold Time, HIGH	1.0				1.0			ns
tH(L)	or LOW Dn to LE	1.0				1.0
tW(H)	Pulse Width,	3.0				3.0			ns
	LE HIGH

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