Fairchild Semiconductor 74ABT244CSJX, 74ABT244CSJ, 74ABT244CSCX, 74ABT244CSC, 74ABT244CPC Datasheet

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Fairchild Semiconductor 74ABT244CSJX, 74ABT244CSJ, 74ABT244CSCX, 74ABT244CSC, 74ABT244CPC Datasheet

May 1992

Revised November 1999

74ABT244

Octal Buffer/Line Driver with 3-STATE Outputs

General Description

The ABT244 is an octal buffer and line driver with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus-oriented transmitter/ receiver.

Features

Non-inverting buffers

Output sink capability of 64 mA, source capability of 32 mA

Guaranteed output skew

Guaranteed multiple output switching specifications

Output switching specified for both 50 pF and 250 pF loads

Guaranteed simultaneous switching, noise level and dynamic threshold performance

Guaranteed latchup protection

High impedance glitch free bus loading during entire power up and power down cycle

Nondestructive hot insertion capability

Disable time less than enable time to avoid bus contention

Ordering Code:

Order Number

Package Number

Package Description

 

 

 

74ABT244CSC

M20B

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body

 

 

 

74ABT244CSJ

M20D

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

 

 

 

74ABT244CMSA

MSA20

20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide

 

 

 

74ABT244CMTC

MTC20

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

 

 

 

74ABT244CPC

N20A

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

 

 

 

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin Names

 

 

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1,

 

 

2

Output Enable Input

 

 

 

 

OE

OE

 

 

 

 

 

 

 

 

 

 

 

 

(Active LOW)

 

 

 

 

 

I0–I7

 

Inputs

 

 

 

 

 

 

 

 

O0–O7

 

Outputs

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Truth Table

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OE1

 

I0–3

O0–3

 

OE2

 

I4–7

O4–7

 

 

 

 

H

 

 

X

Z

 

H

 

X

Z

 

 

 

 

L

 

H

H

 

L

 

H

H

 

 

 

 

L

 

L

L

 

L

 

L

L

 

 

 

 

 

 

 

 

 

 

 

 

H = HIGH Voltage Level

 

 

 

 

 

 

 

 

L = LOW Voltage Level

 

 

 

 

 

 

 

 

X = Immaterial

 

 

 

 

 

 

 

 

 

Z = High Impedance

 

 

 

 

 

 

 

 

Outputs STATE-3 with Driver Buffer/Line Octal 74ABT244

© 1999 Fairchild Semiconductor Corporation

DS010992

www.fairchildsemi.com

74ABT244

Absolute Maximum Ratings(Note 1)

Storage Temperature

− 65° C to + 150° C

Ambient Temperature under Bias

− 55° C to + 125° C

Junction Temperature under Bias

− 55° C to + 150° C

VCC Pin Potential to Ground Pin

− 0.5V to + 7.0V

Input Voltage (Note 2)

− 0.5V to + 7.0V

Input Current (Note 2)

− 30 mA to + 5.0 mA

Voltage Applied to Any Output

 

in the Disabled or

 

Power-Off State

− 0.5V to 5.5V

in the HIGH State

− 0.5V to VCC

Current Applied to Output

 

in LOW State (Max)

twice the rated IOL (mA)

DC Latchup Source Current

− 500 mA

Over Voltage Latchup (I/O)

10V

Recommended Operating

Conditions

Free Air Ambient Temperature

− 40° C to + 85° C

Supply Voltage

+ 4.5V to + 5.5V

Minimum Input Edge Rate (∆ V/∆ t)

 

Data Input

50 mV/ns

Enable Input

20 mV/ns

Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.

Note 2: Either voltage limit or current limit is sufficient to protect inputs.

DC Electrical Characteristics

Symbol

Parameter

Min

Typ

Max

Units

VCC

 

 

 

 

 

Conditions

VIH

Input HIGH Voltage

 

2.0

 

 

V

 

 

 

Recognized HIGH Signal

VIL

Input LOW Voltage

 

 

 

0.8

V

 

 

 

Recognized LOW Signal

VCD

Input Clamp Diode Voltage

 

 

− 1.2

V

Min

 

IIN =

− 18 mA

 

VOH

Output HIGH Voltage

 

2.5

 

 

V

Min

 

IOH =

3 mA

 

 

 

 

2.0

 

 

V

Min

 

IOH =

32 mA

 

VOL

Output LOW Voltage

 

 

 

0.55

 

 

 

 

IOL =

64 mA

 

IIH

Input HIGH Current

 

 

 

1

µ A

Max

 

VIN =

2.7V (Note 4)

 

 

 

 

 

 

1

 

 

 

 

VIN =

VCC

 

IBVI

Input HIGH Current Breakdown Test

 

 

7

µ A

Max

 

VIN =

7.0V

 

IIL

Input LOW Current

 

 

 

− 1

µ A

Max

 

VIN =

0.5V (Note 4)

 

 

 

 

 

 

− 1

 

VIN =

0.0V

 

 

 

 

 

 

 

 

 

 

 

VID

Input Leakage Test

 

4.75

 

 

V

 

0.0

IID =

1.9 µ A

 

 

 

 

 

 

 

 

 

 

 

All Other Pins Grounded

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IOZH

Output Leakage Current

 

 

10

µ A

0 −

5.5V

 

VOUT =

2.7V;

 

n =

 

 

 

 

OE

2.0V

IOZL

Output Leakage Current

 

 

− 10

µ A

0 −

5.5V

 

VOUT =

0.5V;

 

n =

 

 

 

 

OE

2.0V

IOS

Output Short-Circuit Current

− 100

 

− 275

mA

Max

 

VOUT =

0.0V

 

ICEX

Output High Leakage Current

 

 

50

µ A

Max

 

VOUT =

VCC

 

IZZ

Bus Drainage Test

 

 

 

100

µ A

 

0.0

 

VOUT =

5.5V; All Others GND

ICCH

Power Supply Current

 

 

50

µ A

Max

All Outputs HIGH

 

ICCL

Power Supply Current

 

 

30

mA

Max

All Outputs LOW

 

ICCZ

Power Supply Current

 

 

50

µ A

Max

 

 

 

n =

 

 

 

 

 

 

 

OE

VCC,

 

 

 

 

 

 

 

 

 

 

 

All Others at VCC or Ground

ICCT

Additional ICC/Input

Outputs Enabled

 

 

2.5

mA

 

 

 

VI =

VCC − 2.1V

 

 

 

Outputs 3-STATE

 

 

2.5

mA

Max

 

Enable Input VI = VCC − 2.1V

 

 

Outputs 3-STATE

 

 

50

µ A

 

 

 

Data Input VI = VCC − 2.1V

 

 

 

 

 

 

 

 

 

 

All Others at VCC or Ground

ICCD

Dynamic ICC

No Load

 

 

 

mA/

Max

 

Outputs OPEN

 

 

(Note 4)

 

 

 

0.1

MHz

 

 

n =

 

 

 

 

 

 

 

 

 

 

 

OE

GND, (Note 3)

 

 

 

 

 

 

 

 

 

 

One Bit Toggling, 50% Duty Cycle

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note 3: For 8 bits toggling, ICCD <

0.8 mA/MHz.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note 4: Guaranteed, but not tested.

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DC Electrical Characteristics

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

74ABT244

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(SOIC package)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Conditions

 

 

Symbol

 

Parameter

 

 

Min

Typ

Max

 

Units

VCC

 

 

CL =

50 pF,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RL =

500

 

 

VOLP

Quiet Output Maximum Dynamic VOL

 

 

 

0.5

 

0.8

 

V

5.0

 

TA =

25° C (Note 5)

 

 

 

VOLV

Quiet Output Minimum Dynamic VOL

 

 

1.3

− 0.8

 

 

 

V

5.0

 

TA =

25° C (Note 5)

 

 

 

VOHV

Minimum HIGH Level Dynamic Output Voltage

 

2.7

3.1

 

 

 

V

5.0

 

TA =

25° C (Note 7)

 

 

 

VIHD

Minimum HIGH Level Dynamic Input Voltage

 

2.0

1.5

 

 

 

V

5.0

 

TA =

25° C (Note 6)

 

 

 

VILD

Maximum LOW Level Dynamic Input Voltage

 

 

 

1.1

 

0.8

 

V

5.0

 

TA =

25° C (Note 6)

 

 

 

Note 5: Max number of outputs defined as (n). n −

1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.

 

 

 

 

 

 

Note 6: Max number of data inputs (n) switching. n − 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD).

 

 

Guaranteed, but not tested.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note 7: Max number of outputs defined as (n). n −

1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.

 

 

 

 

 

 

AC Electrical Characteristics

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(SOIC and SSOP package)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TA = + 25° C

 

 

TA = −

55° C to +

125° C

TA = − 40° C to + 85° C

 

 

 

 

Symbol

 

Parameter

 

 

VCC = + 5V

 

 

VCC =

4.5V–5.5V

VCC =

4.5V–5.5V

 

Units

 

 

 

 

 

CL = 50 pF

 

 

CL = 50 pF

CL = 50 pF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Min

Typ

Max

 

Min

 

Max

Min

 

Max

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tPLH

 

Propagation Delay

 

1.0

2.5

 

3.6

 

1.0

 

 

 

5.3

1.0

 

 

3.6

 

ns

 

 

tPHL

 

Data to Outputs

 

1.0

2.3

 

3.6

 

1.0

 

 

 

5.0

1.0

 

 

3.6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tPZH

 

Output Enable

 

1.5

3.5

 

6.0

 

0.8

 

 

 

6.5

1.5

 

 

6.0

 

ns

 

 

tPZL

 

Time

 

1.5

3.6

 

6.0

 

1.2

 

 

 

7.9

1.5

 

 

6.0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tPHZ

 

Output Disable

 

1.7

3.5

 

5.6

 

1.2

 

 

 

7.6

1.7

 

 

5.6

 

ns

 

 

tPLZ

 

Time

 

1.7

3.3

 

5.6

 

1.0

 

 

 

7.9

1.7

 

 

5.6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Extended AC Electrical Characteristics

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(SOIC package)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TA40° C to + 85° C

 

TA = − 40° C to + 85° C

TA = − 40° C to + 85° C

 

 

 

 

 

 

 

 

VCC = 4.5V–5.5V

 

 

VCC =

4.5V–5.5V

VCC =

4.5V–5.5V

 

 

 

 

 

Symbol

 

Parameter

 

 

CL = 50 pF

 

 

CL = 250 pF

CL = 250 pF

 

Units

 

 

 

 

 

 

8 Outputs Switching

 

1 Output Switching

8 Outputs Switching

 

 

 

 

 

 

 

 

 

(Note 8)

 

 

 

(Note 9)

 

(Note 10)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Min

Typ

Max

 

Min

 

Max

Min

 

Max

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

fTOGGLE

 

Max Toggle Frequency

 

 

100

 

 

 

 

 

 

 

 

 

 

 

 

 

MHz

 

 

tPLH

 

Propagation Delay

 

1.5

 

 

5.0

 

1.5

 

 

 

6.0

2.5

 

 

8.5

 

ns

 

 

tPHL

 

Data to Outputs

 

1.5

 

 

5.0

 

1.5

 

 

 

6.0

2.5

 

 

8.5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tPZH

 

Output Enable Time

 

1.5

 

 

6.5

 

2.5

 

 

 

7.5

2.5

 

 

10.0

 

ns

 

 

tPZL

 

 

 

1.5

 

 

6.5

 

2.5

 

 

 

7.5

2.5

 

 

12.0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tPHZ

 

Output Disable Time

 

1.0

 

 

5.6

 

 

(Note 11)

 

(Note 11)

 

ns

 

 

tPLZ

 

 

 

1.0

 

 

5.6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note 8: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).

Note 9: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only.

Note 10: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.

Note 11: The 3-STATE delays are dominated by the RC network (500Ω , 250 pF) on the output and have been excluded from the datasheet.

3

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