August 1989
Revised August 2000
100329
Low Power Octal ECL/TTL Bidirectional Translator with Register
General Description
The 100329 is an octal registered bidirectional translator designed to convert TTL logic levels to 100K ECL logic levels and vice versa. The direction of the translation is determined by the DIR input. A LOW on the output enable input (OE) holds the ECL outputs in a cut-off state and the TTL outputs at a high impedance level. The outputs change synchronously with the rising edge of the clock input (CP) even though only one output is enabled at the time.
The cut-off state is designed to be more negative than a normal ECL LOW level. This allows the output emitter-fol- lowers to turn off when the termination supply is − 2.0V, presenting a high impedance to the data bus. This high impedance reduces the termination power and prevents loss of low state noise margin when several loads share the bus.
The 100329 is designed with FAST TTL output buffers, featuring optimal DC drive and capable of quickly charging and discharging highly capacitive loads. All inputs have 50 kΩ pull-down resistors.
Features
■Bidirectional translation
■ECL high impedance outputs
■Registered outputs
■FAST TTL outputs
■3-STATE outputs
■Voltage compensated operating range = − 4.2V to − 5.7V
■High drive IOS
Ordering Code:
Order Number |
Package Number |
Package Description |
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100329PC |
N24E |
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide |
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100329QC |
V28A |
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square |
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100329QI |
V28A |
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square |
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Industrial Temperature Range (− 40° C to + 85° C) |
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Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagrams
24-Pin DIP 28-Pin PLCC
FAST is a registered trademark of Fairchild Semiconductor Corporation.
Register with Translator Bidirectional ECL/TTL Octal Power Low 100329
© 2000 Fairchild Semiconductor Corporation |
DS010583 |
www.fairchildsemi.com |
100329
Logic Symbol
Pin Descriptions
Pin Names |
Description |
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E0–E7 |
ECL Data I/O |
T0–T7 |
TTL Data I/O |
OE |
Output Enable Input |
CP |
Clock Pulse Input (Active Rising Edge) |
DIR |
Direction Control Input |
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All pins function at 100K ECL levels except for T0–T7.
Truth Table
OE |
DIR |
CP |
ECL |
TTL |
Notes |
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Port |
Port |
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L |
L |
X |
Input |
Z |
(Note 1)(Note 3) |
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L |
H |
X |
LOW |
Input |
(Note 2)(Note 3) |
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(Cut-Off) |
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H |
L |
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L |
L |
(Note 1) |
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H |
L |
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H |
H |
(Note 1) |
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H |
L |
L |
X |
NC |
(Note 1)(Note 3) |
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H |
H |
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L |
L |
(Note 2) |
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H |
H |
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H |
H |
(Note 2) |
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H |
H |
L |
NC |
X |
(Note 2)(Note 3) |
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance
= LOW-to-HIGH Clock Transition
NC = No Change
Note 1: ECL input to TTL output mode.
Note 2: TTL input to ECL output mode.
Note 3: Retains data present before CP.
Functional Diagram
Note: DIR and OE use ECL logic levels
Detail
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 4)
Storage Temperature (TSTG) |
− 65° C to + 150° C |
Maximum Junction Temperature (Tj) |
+ 150° C |
VEE Pin Potential to Ground Pin |
− 7.0V to + 0.5V |
VTTL Pin Potential to Ground Pin |
− 0.5V to + 6.0V |
ECL Input Voltage (DC) |
VEE to + 0.5V |
ECL Output Current |
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(DC Output HIGH) |
− 50 mA |
TTL Input Voltage (Note 6) |
− 0.5V to + 6.0V |
TTL Input Current (Note 6) |
− 30 mA to + 5.0 mA |
Voltage Applied to Output |
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in HIGH State |
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3-STATE Output |
− 0.5V to + 5.5V |
Current Applied to TTL |
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Output in LOW State (Max) |
twice the rated IOL (mA) |
ESD (Note 5) |
≥ 2000V |
Recommended Operating
Conditions
Case Temperature (TC) |
0° C to + 85° C |
ECL Supply Voltage (VEE) |
− 5.7V to − 4.2V |
TTL Supply Voltage (VTTL) |
+ 4.5V to + 5.5V |
Note 4: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation.
Note 5: ESD testing conforms to MIL-STD-883, Method 3015.
Note 6: Either voltage limit or current limit is sufficient to protect inputs.
TTL-to-ECL DC Electrical Characteristics
VEE = − 4.2V to − 5.7V, VCC = VCCA = GND, TC = |
0° C to + 85° C, VTTL = |
+ 4.5V to + 5.5V (Note 7) |
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Symbol |
Parameter |
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Min |
Typ |
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Max |
Units |
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Conditions |
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VOH |
Output HIGH Voltage |
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− |
1025 |
− 955 |
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− 870 |
mV |
VIN = |
VIH (Max) or VIL (Min) |
VOL |
Output LOW Voltage |
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− |
1830 |
− 1705 |
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− 1620 |
mV |
Loading with 50Ω to − 2V |
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Cutoff Voltage |
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OE or DIR LOW, |
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− 2000 |
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− 1950 |
mV |
VIN = |
VIH (Max) or VIL (Min) |
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Loading with 50Ω to − 2V |
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VOHC |
Output HIGH Voltage |
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− |
1035 |
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mV |
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Corner Point HIGH |
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VIN = |
VIH (Min) or VIL (Max) |
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VOLC |
Output LOW Voltage |
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− 1610 |
mV |
Loading with 50Ω to − 2V |
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Corner Point LOW |
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VIH |
Input HIGH Voltage |
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2.0 |
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5.0 |
V |
Over VTTL, VEE, TC Range |
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VIL |
Input LOW Voltage |
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0 |
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0.8 |
V |
Over VTTL, VEE, TC Range |
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IIH |
Input HIGH Current |
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70 |
µ A |
VIN = |
+ 2.7V |
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Breakdown Test |
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1.0 |
mA |
VIN = |
+ 5.5V |
IIL |
Input LOW Current |
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− 700 |
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µ A |
VIN = |
+ 0.5V |
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VFCD |
Input Clamp |
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− 1.2 |
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V |
IIN = − 18 mA |
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Diode Voltage |
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IEE |
VEE Supply Current |
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LE LOW, OE and DIR HIGH |
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Inputs Open |
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− 189 |
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− 94 |
mA |
VEE = |
− 4.2V to − 4.8V |
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− 199 |
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− 94 |
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VEE = |
− 4.2V to − 5.7V |
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Note 7: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions.
100329
3 |
www.fairchildsemi.com |
100329
ECL-to-TTL DC Electrical Characteristics
VEE = − 4.2V to − 5.7V, VCC = VCCA = |
GND, TC = 0° C to + 85° C, CL = |
50 pF, VTTL = |
+ 4.5V to + 5.5V (Note 8) |
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Symbol |
Parameter |
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Min |
Typ |
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Max |
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Units |
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Conditions |
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VOH |
Output HIGH Voltage |
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2.7 |
3.1 |
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V |
IOH = |
− |
3 mA, VTTL = |
4.75V |
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2.4 |
2.9 |
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V |
IOH = |
− |
3 mA, VTTL = |
4.50V |
VOL |
Output LOW Voltage |
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0.3 |
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0.5 |
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V |
IOL = |
24 mA, VTTL = |
4.50V |
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VIH |
Input HIGH Voltage |
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− |
1165 |
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− 870 |
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mV |
Guaranteed HIGH Signal |
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for All Inputs |
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VIL |
Input LOW Voltage |
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− |
1830 |
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− 1475 |
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mV |
Guaranteed LOW Signal |
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for All Inputs |
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IIH |
Input HIGH Current |
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350 |
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µ A |
VIN = |
VIH (Max) |
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IIL |
Input LOW Current |
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0.50 |
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µ A |
VIN = |
VIL (Min) |
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IOZHT |
3-STATE Current |
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70 |
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µ A |
VOUT = |
+ 2.7V |
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Output HIGH |
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IOZLT |
3-STATE Current |
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− 700 |
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µ A |
VOUT = |
+ 0.5V |
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Output LOW |
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IOS |
Output Short-Circuit |
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− 225 |
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− 100 |
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mA |
VOUT = |
0.0V, VTTL = |
+ 5.5V |
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Current |
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ITTL |
VTTL Supply Current |
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74 |
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mA |
TTL Outputs LOW |
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49 |
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mA |
TTL Outputs HIGH |
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67 |
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mA |
TTL Outputs in 3-STATE |
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Note 8: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions.
DIP TTL-to-ECL AC Electrical Characteristics
VEE = − 4.2V to − 5.7V, VTTL = + |
4.5V to + 5.5V, VCC = |
VCCA = |
GND |
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Symbol |
Parameter |
TC = 0° C |
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TC = 25° C |
TC = 85° C |
Units |
Conditions |
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Min |
Max |
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Min |
Max |
Min |
Max |
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fMAX |
Max Toggle Frequency |
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350 |
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350 |
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350 |
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MHz |
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tPLH |
CP to En |
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1.7 |
3.6 |
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1.7 |
3.7 |
1.9 |
3.9 |
ns |
Figures 1, 2 |
tPHL |
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tPZH |
OE to En |
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1.3 |
4.2 |
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1.5 |
4.4 |
1.7 |
4.8 |
ns |
Figures 1, 2 |
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(Cutoff to HIGH) |
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tPHZ |
OE to En |
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1.5 |
4.5 |
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1.6 |
4.5 |
1.6 |
4.6 |
ns |
Figures 1, 2 |
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(HIGH to Cutoff) |
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tPHZ |
DIR to En |
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1.6 |
4.3 |
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1.6 |
4.3 |
1.7 |
4.5 |
ns |
Figures 1, 2 |
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(HIGH to Cutoff) |
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tSET |
Tn to CP |
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1.1 |
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1.1 |
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1.1 |
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ns |
Figures 1, 2 |
tHOLD |
Tn to CP |
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1.7 |
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1.7 |
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1.9 |
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ns |
Figures 1, 2 |
tPW(H) |
Pulse Width CP |
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2.1 |
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2.1 |
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2.1 |
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ns |
Figures 1, 2 |
tTLH |
Transition Time |
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0.6 |
1.6 |
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0.6 |
1.6 |
0.6 |
1.6 |
ns |
Figures 1, 2 |
tTHL |
20% to 80%, 80% to 20% |
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www.fairchildsemi.com |
4 |
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