Fairchild Semiconductor 100355QIX, 100355QI, 100355QCX, 100355QC, 100355PC Datasheet

July 1989

Revised August 2000

100355

Low Power Quad Multiplexer/Latch

General Description

The 100355 contains four transparent latches, each of which can accept and store data from two sources. When both Enable (En) inputs are LOW, the data that appears at an output is controlled by the Select (Sn) inputs, as shown in the Operating Mode table. In addition to routing data from either D0 or D1, the Select inputs can force the outputs LOW for the case where the latch is transparent (both Enables are LOW) and can steer a HIGH signal from either D0 or D1 to an output. The Select inputs can be tied together for applications requiring only that data be steered from either D0 or D1. A positive-going signal on either Enable input latches the outputs. A HIGH signal on the Master Reset (MR) input overrides all the other inputs and forces the Q outputs LOW. All inputs have 50 kΩ pull-down resistors.

Features

■Greater than 40% power reduction of the 100155

■2000V ESD protection

■Pin/function compatible with 100155

■Voltage compensated operating range = − 4.2V to − 5.7V

■Available to industrial grade temperature range

Ordering Code:

Order Number	Package Number	Package Description
100355PC	N24E	24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100355QC	V28A	28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100355QI	V28A	28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
		Industrial Temperature Range (− 40° C to + 85° C)

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol	Connection Diagrams
	24-Pin DIP

Pin Descriptions

	Pin Names							Description
		1,				2		Enable Inputs (Active LOW)
	E			E
								Select Inputs
	S	0, S1							28-Pin PLCC
	MR							Master Reset
	Dna–Dnd							Data Inputs
	Qa–Qd							Data Outputs
							d	Complementary Data Outputs
	Q		a–Q

Multiplexer/Latch Quad Power Low 100355

© 2000 Fairchild Semiconductor Corporation

DS010147

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100355

Operating Mode Table

Truth Table

Controls

Outputs

Inputs

Outputs

E1

E2

S1

S0

Qn

MR

E1

E2

S1

S0

D1x D0x

Qx

Qx

H

X

X

X

Latched (Note 1)

H

X

X

X

X

X

X

H

L

X

H

X

X

Latched (Note 1)

L

L

L

H

H

H

X

L

H

L

L

L

L

D0x

L

L

L

H H

L X

H

L

L

L

H

L

D0x + D1x

L

L

L

L

L

X H

L

H

L

L

L

H

L

L

L

L

L

L

X

L

H

L

L

L

H

H

D1x

L

L L

L H

X X

H

L

H =

HIGH

Voltage Level

L

L

L

H

L

H

X

L

H

L = LOW Voltage Level

X = Don’t Care

L

L

L

H

L

X

H

L

H

Note 1: Stores data present before

E

went HIGH

L

L

L

H

L

L

L

H

L

L

H

X

X

X

X

X

Latched (Note 1)

L

X

H

X

X

X

X

Latched (Note 1)

Logic Diagram

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2

Absolute Maximum Ratings(Note 2)

Storage Temperature (TSTG)	− 65° C to + 150° C
Maximum Junction Temperature (TJ)	+ 150° C
VEE Pin Potential to Ground Pin	− 7.0V to + 0.5V
Input Voltage (DC)	VEE to + 0.5V
Output Current (DC Output HIGH)	− 50 mA
ESD (Note 3)	≥ 2000V

Recommended Operating

Conditions

Case Temperature (TC)
Commercial	0° C to + 85° C
Industrial	− 40° C to + 85° C
Supply Voltage (VEE)	− 5.7V to − 4.2V

Note 2: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Note 3: ESD testing conforms to MIL-STD-883, Method 3015.

Commercial Version

DC Electrical Characteristics (Note 4)

VEE = − 4.2V to − 5.7V, VCC = VCCA =

GND, TC = 0° C to + 85° C

Symbol

Parameter

Min

Typ

Max

Units

Conditions

VOH

Output HIGH Voltage

− 1025

− 955

− 870

mV

VIN =

VIH (Max)

Loading with

VOL

Output LOW Voltage

− 1830

− 1705

− 1620

mV

or VIL (Min)

50Ω

to − 2.0V

VOHC

Output HIGH Voltage

− 1035

mV

VIN =

VIH (Min)

Loading with

VOLC

Output LOW Voltage

− 1610

mV

or VIL (Max)

50Ω

to − 2.0V

VIH

Input HIGH Voltage

− 1165

− 870

mV

Guaranteed HIGH Signal

for ALL Inputs

VIL

Input LOW Voltage

− 1830

− 1475

mV

Guaranteed LOW Signal

for ALL Inputs

IIL

Input LOW Current

0.50

µ A

VIN =

VIL (Min)

IIH

Input HIGH Current

S

0, S1

220

µ A

VIN =

E1, E2

350

VIH (Max)

Dna–Dnd

340

MR

430

IEE

Power Supply Current

− 87

− 40

mA

Inputs Open

Note 4: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions.

100355

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