January 1993
Revised November 1999
74ABT377
Octal D-Type Flip-Flop with Clock Enable
General Description
The ABT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously when the Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.
Features
■Clock enable for address and data synchronization applications
■Eight edge-triggered D-type flip-flops
■Buffered common clock
■See ABT273 for master reset version
■See ABT373 for transparent latch version
■See ABT374 for 3-STATE version
■Output sink capability of 64 mA, source capability of 32 mA
■Guaranteed latchup protection
■High impedance glitch free bus loading during entire power up and power down cycle
■Non-destructive hot insertion capability
■Disable time less than enable time to avoid bus contention
Ordering Code:
Order Number |
Package Number |
Package Description |
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74ABT377CSC |
M20B |
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body |
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74ABT377CSJ |
M20D |
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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74ABT377CMSA |
MSA20 |
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide |
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74ABT377CMTC |
MTC20 |
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram |
Pin Descriptions |
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Pin Names |
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Descriptions |
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D0–D7 |
Data Inputs |
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CE |
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Clock Enable (Active LOW) |
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CP |
Clock Pulse Input |
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Q0–Q7 |
Data Outputs |
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Truth Table |
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Operating Mode |
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Inputs |
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Output |
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CP |
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CE |
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Dn |
Qn |
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Load “1” |
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I |
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h |
H |
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Load “0” |
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I |
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I |
L |
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Hold |
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h |
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X |
No Change |
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(Do Nothing) |
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X |
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H |
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X |
No Change |
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H = |
HIGH Voltage Level |
L = |
LOW Voltage Level |
X = |
Immaterial |
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LOW-to-HIGH Clock Transition |
h = |
HIGH Voltage Level one setup time prior to the |
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LOW-to-HIGH Clock Transition |
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I = |
LOW Voltage Level one setup time prior to the |
LOW-to-HIGH Clock Transition
Enable Clock with Flop-Flip Type-D Octal 74ABT377
© 1999 Fairchild Semiconductor Corporation |
DS011550 |
www.fairchildsemi.com |
74ABT377
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 1)
Storage Temperature |
− 65° C to + 150° C |
Ambient Temperature under Bias |
− 55° C to + 125° C |
Junction Temperature under Bias |
− 55° C to + 150° C |
VCC Pin Potential to Ground Pin |
− 0.5V to + 7.0V |
Input Voltage (Note 2) |
− 0.5V to + 7.0V |
Input Current (Note 2) |
− 30 mA to + 5.0 mA |
Voltage Applied to Any Output |
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in the Disabled or |
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Power-OFF State |
− 0.5V to + 4.75V |
in the HIGH State |
− 0.5V to VCC |
Current Applied to Output |
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in LOW State (Max) |
Twice the rated IOL (mA) |
DC Latchup Source Current |
− 500 mA |
(Across Comm Operating Range) |
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Over Voltage Latchup |
VCC + 4.5V |
Recommended Operating
Conditions
Free Air Ambient Temperature |
− 40° C to + 85° C |
Supply Voltage |
+ 4.5V to + 5.5V |
Minimum Input Edge Rate (∆ V/∆ t) |
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Data Input |
50 mV/ns |
Enable Input |
20 mV/ns |
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs
DC Electrical Characteristics
Symbol |
Parameter |
Min |
Typ |
Max |
Units |
VCC |
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Conditions |
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VIH |
Input HIGH Voltage |
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2.0 |
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V |
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Recognized HIGH Signal |
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VIL |
Input LOW Voltage |
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0.8 |
V |
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Recognized LOW Signal |
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VCD |
Input Clamp Diode Voltage |
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− 1.2 |
V |
Min |
IIN = |
− 18 mA |
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VOH |
Output HIGH Voltage |
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2.5 |
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V |
Min |
IOH = |
− |
3 mA |
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2.0 |
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IOH = |
− |
32 mA |
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VOL |
Output LOW Voltage |
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0.55 |
V |
Min |
IOL = |
64 mA |
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IIH |
Input HIGH Current |
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1 |
µ A |
Max |
VIN = |
2.7V (Note 3) |
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1 |
VIN = |
VCC |
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IBVI |
Input HIGH Current |
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7 |
µ A |
Max |
VIN = |
7.0V |
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Breakdown Test |
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IIL |
Input LOW Current |
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− 1 |
µ A |
Max |
VIN = |
0.5V (Note 3) |
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− 1 |
VIN = |
0.0V |
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VID |
Input Leakage Test |
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4.75 |
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V |
0.0 |
IID = |
1.9 µ A |
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All Other Pins Grounded |
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IOS |
Output Short-Circuit Current |
− 100 |
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− 275 |
mA |
Max |
VOUT = |
0.0V |
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ICEX |
Output HIGH Leakage Current |
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50 |
µ A |
Max |
VOUT = |
VCC |
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ICCH |
Power Supply Current |
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50 |
µ A |
Max |
All Outputs HIGH |
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ICCL |
Power Supply Current |
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30 |
mA |
Max |
All Outputs LOW |
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ICCT |
Maximum ICC/Input |
Outputs Enabled |
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VI = |
VCC − 2.1V |
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1.5 |
mA |
Max |
Data Input VI = VCC − 2.1V |
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All Others at VCC or GND |
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ICCD |
Dynamic ICC |
No Load |
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0.3 |
mA/ |
Max |
Outputs Open (Note 4) |
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MHz |
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One bit Toggling, 50% Duty Cycle |
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Note 3: Guaranteed but not tested.
Note 4: For 8 bits toggling, ICCD < 0.5 mA/MHz.
74ABT377
3 |
www.fairchildsemi.com |