February 1990
Revised August 2000
100370
Low Power Universal Demultiplexer/Decoder
General Description
The 100370 universal demultiplexer/decoder functions as either a dual 1-of-4 decoder or as a single 1-of-8 decoder, depending on the signal applied to the Mode Control (M) input. In the dual mode, each half has a pair of active-LOW Enable (E) inputs. Pin assignments for the E inputs are such that in the 1-of-8 mode they can easily be tied together in pairs to provide two active-LOW enables (E1a to
E1b, E2a to E2b). Signals applied to auxiliary inputs Ha, Hb and Hc determine whether the outputs are active HIGH or
active LOW. In the dual 1-of-4 mode the Address inputs are A0a, A1a and A0b, A1b with A2a unused (i.e., left open, tied to VEE or with LOW signal applied). In the 1-of-8 mode, the
Address inputs are A0a, A1a, A2a with A0b and A1b LOW or OPEN. All inputs have 50 kΩ pull-down resistors.
Features
■35% power reduction of the 100170
■2000V ESD protection
■Pin/function compatible with 100170
■Voltage compensated operating range = − 4.2V to − 5.7V
Ordering Code:
Order Number |
Package Number |
Package Description |
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100370PC |
N24E |
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide |
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100370QC |
V28A |
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square |
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100370QI |
V28A |
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square |
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Industrial Temperature Range (− 40° C to + 85° C) |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
24-Pin DIP 28-Pin PLCC
Demultiplexer/Decoder Universal Power Low 100370
© 2000 Fairchild Semiconductor Corporation |
DS010649 |
www.fairchildsemi.com |
100370
Logic Symbols |
Pin Descriptions |
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Single 1-of 8 Application |
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Pin Names |
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Description |
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Ana, Anb |
Address Inputs |
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E |
na, |
E |
nb |
Enable Inputs |
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M |
Mode Control Input |
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Ha |
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Z0–Z3 (Z |
0a–Z3a) Polarity Select Input |
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Hb |
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Z4–Z7 (Z |
0b–Z3b) Polarity Select Input |
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Hc |
Common Polarity Select Input |
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Z0–Z7 |
Single 1-of-8 Data Outputs |
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Dual 1-of-4 Application- |
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Zna, Znb |
Dual 1-of-4 Data Outputs |
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Truth Tables
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Dual 1-of-4 Mode (M = |
A2a = |
Hc = |
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LOW) |
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Inputs |
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Active HIGH Outputs |
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Active LOW Outputs |
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(Ha and Hb Inputs HIGH) |
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(Ha and Hb Inputs LOW) |
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E1a |
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E2a |
A1a |
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A0a |
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Z0a |
Z1a |
Z2a |
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Z3a |
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Z0a |
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Z1a |
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Z2a |
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Z3a |
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E1b |
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E2b |
A1b |
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A0b |
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Z0b |
Z1b |
Z2b |
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Z3b |
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Z0b |
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Z1b |
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Z2b |
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Z3b |
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H |
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H |
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Single 1-of-8 Mode (M = |
HIGH; A0b = |
A1b = |
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Ha = Hb = LOW) |
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Inputs |
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Active HIGH Outputs (Note 1) |
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(Hc Input HIGH) |
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E1 |
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E2 |
A2a |
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A1a |
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A0a |
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Z0 |
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Z1 |
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Z3 |
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Z4 |
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Z5 |
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Z7 |
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H = HIGH Voltage Level |
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LOW Voltage Level |
X = Don’t Care |
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1 = |
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1a and |
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1b wired; |
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2 = |
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E |
E |
E |
E |
E22a and E2b wired |
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Note 1: for Hc = LOW, output states are complemented
www.fairchildsemi.com |
2 |
Logic Diagram
(Zn) for 1-of-4 applications.
100370
3 |
www.fairchildsemi.com |
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