Fairchild Semiconductor 100336SCX, 100336SC, 100336QIX, 100336QI, 100336QCX Datasheet

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August 1989

Revised August 2000

100336

Low Power 4-Stage Counter/Shift Register

General Description

The 100336 operates as either a modulo-16 up/down counter or as a 4-bit bidirectional shift register. Three Select (Sn) inputs determine the mode of operation, as shown in the Function Select table. Two Count Enable (CEP, CET) inputs are provided for ease of cascading in multistage counters. One Count Enable (CET) input also doubles as a Serial Data (D0) input for shift-up operation. For shift-down operation, D3 is the Serial Data input. In

counting operations the Terminal Count (TC) output goes LOW when the counter reaches 15 in the count/up mode or 0 (zero) in the count/down mode. In the shift modes, the TC output repeats the Q3 output. The dual nature of this TC/Q3

output and the D0/CET input means that one interconnection from one stage to the next higher stage serves as the link for multistage counting or shift-up operation. The indi-

vidual Preset (Pn) inputs are used to enter data in parallel or to preset the counter in programmable counter applications. A HIGH signal on the Master Reset (MR) input overrides all other inputs and asynchronously clears the flipflops. In addition, a synchronous clear is provided, as well as a complement function which synchronously inverts the contents of the flip-flops. All inputs have 50 kΩ pull-down resistors.

Features

■40% power reduction of the 100136

■2000V ESD protection

■Pin/function compatible with 100136

■Voltage compensated operating range = − 4.2V to − 5.7V

■Available to industrial grade temperature range

Ordering Code:

Order Number	Package Number	Package Description

100336SC	M24B	24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

100336PC	N24E	24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide

100336QC	V28A	28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

100336QI	V28A	28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
		Industrial Temperature Range (− 40° C to + 85° C)

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagrams

24-Pin DIP/SOIC 28-Pin PLCC

Logic Symbol

DS010584

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100336

Function Select Table

Pin Descriptions

S2	S1	S0	Function
L	L	L	Parallel Load
L	L	H	Complement
L	H	L	Shift Left
L	H	H	Shift Right
H	L	L	Count Down
H	L	H	Clear
H	H	L	Count Up
H	H	H	Hold

Pin Names				Description

CP				Clock Pulse Input
				Count Enable Parallel Input (Active LOW)
CEP
				Serial Data Input/Count Enable
D0		/CET
				Trickle Input (Active LOW)
S0–S2				Select Inputs
MR				Master Reset Input
P0–P3				Preset Inputs
D3				Serial Data Input
TC				Terminal Count Output
Q0–Q3				Data Outputs
			3	Complementary Data Outputs
Q	0–Q

Truth Table

Q0 = LSB

Inputs

Outputs

CEP

D0/CET

Mode

Preset (Parallel Load)

Invert

Shift to LSB

Q3 (Note 1)

Shift to MSB

(Q0–3) minus 1

Count Down

Count Down with

CEP

not active

Count Down with

CET

not active

Clear

(Q0–3) plus 1

Count Up

Count Up with

CEP

not active

Count Up with

CET

not active

Hold

Asynchronous

Master Reset

1 = L if Q0–Q3 =

LLLL

H if Q0–Q3 ≠ LLLL

2 = L if Q0–Q3 = HHHH H if Q0–Q3 ≠ HHHH

H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care

= LOW-to-HIGH Transition

Note 1: Before the clock, TC is Q3

After the clock, TC is Q2

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Logic Diagram

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100336

Absolute Maximum Ratings(Note 2)

Storage Temperature (TSTG)	− 65° C to + 150° C
Maximum Junction Temperature (TJ)	+ 150° C
VEE Pin Potential to Ground Pin	− 7.0V to + 0.5V
Input Voltage (DC)	VEE to + 0.5V
Output Current (DC Output HIGH)	− 50 mA
ESD (Note 3)	≥ 2000V

Recommended Operating

Conditions

Case Temperature (TC)
Commercial	0° C to + 85° C
Industrial	− 40° C to + 85° C
Supply Voltage (VEE)	− 5.7V to − 4.2V

Note 2: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.

Note 3: ESD testing conforms to MIL-STD-883, Method 3015.

Commercial Version

DC Electrical Characteristics (Note 4)

VEE = − 4.2V to − 5.7V, VCC = VCCA =		GND, TC = 0° C to + 85° C
Symbol	Parameter		Min	Typ	Max	Units		Conditions

VOH	Output HIGH Voltage		− 1025	− 955	− 870	mV	VIN = VIH (Max)		Loading with
VOL	Output LOW Voltage		− 1830	− 1705	− 1620	mV	or VIL (Min)		50Ω to − 2.0V
VOHC	Output HIGH Voltage		− 1035			mV	VIN =	VIH(Min)	Loading with
VOLC	Output LOW Voltage				− 1610	mV	or VIL (Max)		50Ω to − 2.0V
VIH	Input HIGH Voltage		− 1165		− 870	mV	Guaranteed HIGH Signal
							for All Inputs

VIL	Input LOW Voltage		− 1830		− 1475	mV	Guaranteed LOW Signal
							for All Inputs

IIL	Input LOW Current		0.50			µ A	VIN =	VIL (Min)
IIH	Input HIGH Current				240	µ A	VIN =	VIH (Max)
IEE	Power Supply Current		− 165		− 80		Inputs Open

Note 4: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions.

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Commercial Version (Continued)

DIP AC Characteristics

VEE = − 4.2V to − 5.7V, VCC = VCCA =				GND
Symbol			Parameter	TC = 0° C		TC = + 25° C		TC = + 85° C		Units	Conditions
				Min	Max	Min	Max	Min	Max

fSHIFT	Shift Frequency			300		300		300		MHz	Figures 2, 3
tPLH	Propagation Delay			1.00	2.00	1.00	2.00	1.00	2.00	ns	Figures 1, 3

tPHL	CP to Qn, Qn										(Note 5)
tPHL	CP to Qn, Qn										(Note 5)
tPLH	Propagation Delay			2.10	3.50	2.10	3.50	2.10	3.70	ns	Figures 1, 7, 8

tPHL	CP to TC (Shift)										(Note 5)
tPHL	CP to TC (Shift)										(Note 5)
tPLH	Propagation Delay			2.40	4.40	2.40	4.40	2.60	4.70	ns	Figures 1, 9
tPHL
	CP to TC (Count)										(Note 5)
	CP to TC (Count)										(Note 5)
tPLH	Propagation Delay			1.40	2.50	1.40	2.50	1.50	2.60	ns	Figures 1, 4

tPHL	MR to Qn, Qn										(Note 5)
tPHL	MR to Qn, Qn										(Note 5)
tPLH	Propagation Delay			2.80	5.10	2.90	5.20	3.10	5.50	ns	Figures 1, 12

tPHL	MR to TC (Count)										(Note 5)
tPHL	MR to TC (Count)										(Note 5)
tPHL	Propagation Delay			2.40	4.00	2.40	4.00	2.50	4.10	ns	Figures 1, 10, 11

	MR to TC (Shift)										(Note 5)
	MR to TC (Shift)										(Note 5)

tPLH	Propagation Delay			1.80	3.10	1.80	3.10	1.90	3.30	ns

tPHL	D0/CET to TC										Figures 1, 5
tPHL	D0/CET to TC										Figures 1, 5
tPLH	Propagation Delay			1.90	4.10	1.90	4.10	2.10	4.40	ns	(Note 5)

tPHL	Sn to TC
tPHL	Sn to TC
tTLH	Transition Time			0.35	1.20	0.35	1.20	0.35	1.20	ns	Figures 1, 3
tTHL	20% to 80%, 80% to 20%			0.35	1.20	0.35	1.20	0.35	1.20	ns	Figures 1, 3
tTHL	20% to 80%, 80% to 20%
tS	Setup Time
		D3		1.00		1.00		1.00
		Pn		1.50		1.50		1.50
		D0	/CET	1.30		1.30		1.30		ns	Figures 6, 4
		CEP		1.40		1.40		1.40
		Sn		3.40		3.40		3.40
		MR (Release Time)		2.60		2.60		2.60

tH	Hold Time
		D3		0.40		0.40		0.40
		Pn		0.30		0.30		0.30		ns	Figure 6
		D0/CET		0.30		0.30		0.30		ns	Figure 6
		D0/CET		0.30		0.30		0.30
		CEP		0.20		0.20		0.20
		Sn		0.10		0.10		0.10

tPW(H)	Pulse Width HIGH			2.00		2.00		2.00		ns	Figures 3, 4
	CP, MR			2.00		2.00		2.00		ns	Figures 3, 4
	CP, MR

Note 5: The propagation delay specified is for single output switching. Delays may vary up to 250 ps with multiple outputs switching.

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