Fairchild Semiconductor 100371SCX, 100371SC, 100371QIX, 100371QI, 100371QCX Datasheet

October 1989

Revised August 2000

100371

Low Power Triple 4-Input Multiplexer with Enable

General Description

The 100371 contains three 4-input multiplexers which share a common decoder (inputs S0 and S1). Output buffer gates provide true and complement outputs. A HIGH on the Enable input (E) forces all true outputs LOW (see Truth Table). All inputs have 50 kΩ pull-down resistors.

Features

■35% power reduction of the 100171

■2000V ESD protection

■Pin/function compatible with 100171

■Voltage compensated operating range = − 4.2V to − 5.7V

■Available to industrial grade temperature range

Ordering Code:

Order Number	Package Number	Package Description
100371SC	M24B	24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
100371PC	N24E	24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
10371QC	V28A	28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
10371QI	V28A	28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
		Industrial Temperature Range (− 40° C to + 85° C)

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol	Connection Diagrams
	24-Pin DIP/SOIC

Pin Descriptions
									28-Pin PLCC
	Pin Names							Description
	I0x–I3x							Data Inputs
	S0, S1							Select Inputs
								Enable Input (Active LOW)
				E
		Za–Zc						Data Outputs
							c	Complementary Data Outputs
		Z	a–Z

Enable with Multiplexer Input-4 Triple Power Low 100371

© 2000 Fairchild Semiconductor Corporation

DS010148

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100371

Truth Table

			Inputs		Outputs
E			S0	S1	Zn
	L		L	L	I0x
	L		H	L	I1x
	L		L	H	I2x
	L		H	H	I3x
H			X	X	L

H = HIGH Voltage Level

L = LOW Voltage Level

X = Don’t Care

Logic Diagram

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2

Absolute Maximum Ratings(Note 1)

Storage Temperature (TSTG)	− 65° C to + 150° C
Maximum Junction Temperature (TJ)	+ 150° C
VEE Pin Potential to Ground Pin	− 7.0V to + 0.5V
Input Voltage (DC)	VEE to + 0.5V
Output current (DC Output HIGH)	− 50 mA
ESD (Note 2)	≥ 2000V

Recommended Operating

Conditions

Case Temperature (TC)
Commercial	0° C to + 85° C
Industrial	− 40° C to + 85° C
Supply Voltage (VEE)	− 5.7V to − 4.2V

Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Note 2: ESD testing conforms to MIL-STD-883, Method 3015.

Commercial Version

DC Electrical Characteristics (Note 3)

VEE = − 4.2V to − 5.7V, VCC = VCCA =

GND, TC = 0° C to + 85° C

Symbol

Parameter

Min

Typ

Max

Units

Conditions

VOH

Output HIGH Voltage

− 1025

− 955

− 870

mV

VIN = VIH (Max)

Loading with

VOL

Output LOW Voltage

− 1830

− 1705

− 1620

mV

or VIL (Min)

50Ω

to − 2.0V

VOHC

Output HIGH Voltage

− 1035

mV

VIN =

VIH (Min)

Loading with

VOLC

Output LOW Voltage

− 1610

mV

or VIL (Max)

50Ω

to − 2.0V

VIH

Input HIGH Voltage

− 1165

− 870

mV

Guaranteed HIGH Signal

for All Inputs

VIL

Input LOW Voltage

− 1830

− 1475

mV

Guaranteed LOW Signal

for All Inputs

IIL

Input LOW Current

0.50

µ A

VIN =

VIL (Min)

IIH

Input HIGH Current

I0X–I3X

340

µ A

VIN =

VIH (Max)

S0, S1, E

300

IEE

Power Supply Current

− 75

− 39

mA

Inputs Open

Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions.

DIP AC Electrical Characteristics

VEE = − 4.2V to − 5.7V, VCC = VCCA = GND

	Symbol			Parameter	TC = 0° C		TC = + 25° C		TC = + 85° C		Units	Conditions
					Min	Max	Min	Max	Min	Max
	tPLH	Propagation Delay			0.45	1.50	0.45	1.50	0.45	1.60	ns
	tPHL	I0x–I3x to Output
	tPLH	Propagation Delay			0.90	2.40	0.90	2.40	1.00	2.60	ns	Figures 1, 2
	tPHL	S0, S1 to Output										(Note 4)
	tPLH	Propagation Delay			0.65	2.30	0.65	2.30	0.75	2.40	ns
	tPHL	E to Output
	tTLH	Transition Time			0.35	1.20	0.35	1.20	0.35	1.20	ns	Figures 1, 2
	tTHL	20% to 80%, 80% to 20%

Note 4: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching.

100371

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