Fairchild Semiconductor 100328SCX, 100328SC, 100328QIX, 100328QI, 100328QCX Datasheet
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April 1989
Revised August 2000
100328
Low Power Octal ECL/TTL Bi-Directional Translator with Latch
General Description
The 100328 is an octal latched bi-directional translator designed to convert TTL logic levels to 100K ECL logic levels and vice versa. The direction of this translation is determined by the DIR input. A LOW on the output enable input (OE) holds the ECL outputs in a cut-off state and the TTL outputs at a high impedance level. A HIGH on the latch enable input (LE) latches the data at both inputs even though only one output is enabled at the time. A LOW on LE makes the 100328 transparent.
The cut-off state is designed to be more negative than a normal ECL LOW level. This allows the output emitter-fol- lowers to turn off when the termination supply is − 2.0V, presenting a high impedance to the data bus. This high impedance reduces termination power and prevents loss of low state noise margin when several loads share the bus.
The 100328 is designed with FAST TTL output buffers, featuring optimal DC drive and capable of quickly charging and discharging highly capacitive loads. All inputs have 50 kΩ pull-down resistors.
Features
■Identical performance to the 100128 at 50% of the supply current
■Bi-directional translation
■2000V ESD protection
■Latched outputs
■FAST TTL outputs
■3-STATE outputs
■Voltage compensated operating range = − 4.2V to − 5.7V
■Available to industrial grade temperature range
Ordering Code:
Order Number |
Package Number |
Package Description |
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100328SC |
M24B |
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide |
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100328PC |
N24E |
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide |
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100328QC |
V28A |
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square |
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100328QI |
V28A |
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square |
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Industrial Temperature Range (− 40° C to + 85° C) |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol |
Pin Descriptions |
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Pin Names |
Description |
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E0–E7 |
ECL Data I/O |
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T0–T7 |
TTL Data I/O |
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OE |
Output Enable Input |
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LE |
Latch Enable Input |
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DIR |
Direction Control Input |
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All pins function at 100K ECL levels except for T0–T7. |
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FAST is a registered trademark of Fairchild Semiconductor Corporation.
Latch with Translator Directional-Bi ECL/TTL Octal Power Low 100328
© 2000 Fairchild Semiconductor Corporation |
DS010219 |
www.fairchildsemi.com |
100328
Connection Diagrams |
Functional Diagram |
24-Pin DIP/SOIC
28-Pin PLCC
Truth Table
OE |
DIR |
LE |
ECL |
TTL |
Notes |
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Port |
Port |
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L |
X |
L |
LOW |
Z |
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(Cut-Off) |
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L |
L |
H |
Input |
Z |
(Note 1)(Note 3) |
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L |
H |
H |
LOW |
Input |
(Note 2)(Note 3) |
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(Cut-Off) |
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H |
L |
L |
L |
L |
(Note 1)(Note 4) |
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H |
L |
L |
H |
H |
(Note 1)(Note 4) |
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H |
L |
H |
X |
Latched |
(Note 1)(Note 3) |
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H |
H |
L |
L |
L |
(Note 2)(Note 4) |
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H |
H |
L |
H |
H |
(Note 2)(Note 4) |
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H |
H |
H |
Latched |
X |
(Note 2)(Note 4) |
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H = |
HIGH Voltage Level |
L = |
LOW Voltage Level |
X = |
Don’t Care |
Z = |
High Impedance |
Note 1: ECL input to TTL output mode.
Note 2: TTL input to ECL output mode.
Note 3: Retains data present before LE set HIGH.
Note 4: Latch is transparent.
Note: LE, DIR, and OE use ECL logic levels
Detail
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 5)
Storage Temperature (TSTG) |
− 65° C to + 150° C |
Maximum Junction Temperature (TJ) |
+ 150° C |
VEE Pin Potential to Ground Pin |
− 7.0V to + 0.5V |
VTTL Pin Potential to Ground Pin |
− 0.5V to + 6.0V |
ECL Input Voltage (DC) |
VEE to + 0.5V |
ECL Output Current |
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(DC Output HIGH) |
− 50 mA |
TTL Input Voltage (Note 6) |
− 0.5V to + 6.0V |
TTL Input Current (Note 6) |
− 30 mA to + 5.0 mA |
Voltage Applied to Output |
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in HIGH State |
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3-STATE Output |
− 0.5V to + 5.5V |
Current Applied to TTL |
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Output in LOW State (Max) |
twice the rated IOL (mA) |
ESD (Note 7) |
≥ 2000V |
Recommended Operating
Conditions
Case Temperature (TC) |
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Commercial |
0° C to + 85° C |
Industrial |
− 40° C to + 85° C |
ECL Supply Voltage (VEE) |
− 5.7V to − 4.2V |
TTL Supply Voltage (VTTL) |
+ 4.5V to + 5.5V |
Note 5: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation.
Note 6: Either voltage limit or current limit is sufficient to protect inputs.
Note 7: ESD testing conforms to MIL-STD-883, Method 3015.
Commercial Version
TTL-to-ECL DC Electrical Characteristics (Note 8)
VEE = − 4.2V to − 5.7V, VCC = VCCA = GND, TC = |
0° C to + 85° C, VTTL = |
+ 4.5V to + 5.5V |
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Symbol |
Parameter |
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Min |
Typ |
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Max |
Units |
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Conditions |
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VOH |
Output HIGH Voltage |
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− 1025 |
− 955 |
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− 870 |
mV |
VIN = |
VIH(Max) or VIL(Min) |
VOL |
Output LOW Voltage |
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− 1830 |
− 1705 |
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− 1620 |
mV |
Loading with 50Ω to − 2V |
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Cutoff Voltage |
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OE or DIR LOW, |
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− 2000 |
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− 1950 |
mV |
VIN = |
VIH(Max) or VIL(Min), |
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Loading with 50Ω to − 2V |
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VOHC |
Output HIGH Voltage |
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− 1035 |
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mV |
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Corner Point HIGH |
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VIN = |
VIH(Min) or VIL(Max) |
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VOLC |
Output LOW Voltage |
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− 1610 |
mV |
Loading with 50Ω to − 2V |
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Corner Point LOW |
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VIH |
Input HIGH Voltage |
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2.0 |
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5.0 |
V |
Over VTTL, VEE, TC Range |
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VIL |
Input LOW Voltage |
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0 |
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0.8 |
V |
Over VTTL, VEE, TC Range |
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IIH |
Input HIGH Current |
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70 |
µ A |
VIN = |
+ 2.7V |
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Breakdown Test |
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1.0 |
mA |
VIN = |
+ 5.5V |
IIL |
Input LOW Current |
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− 700 |
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µ A |
VIN = |
+ 0.5V |
VFCD |
Input Clamp Diode Voltage |
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− 1.2 |
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V |
IIN = − 18 mA |
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IEE |
VEE Supply Current |
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LE LOW, OE and DIR HIGH |
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Inputs OPEN |
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− 159 |
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− 75 |
mA |
VEE = |
− 4.2V to − 4.8V |
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− 169 |
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− 75 |
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VEE = |
− 4.2V to − 5.7V |
Note 8: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions.
100328
3 |
www.fairchildsemi.com |
100328
Commercial Version (Continued)
ECL-to-TTL DC Electrical Characteristics (Note 9)
VEE = − 4.2V to − 5.7V, VCC = VCCA = GND, TC = |
0° C to + 85° C, CL = |
50 pF, VTTL = |
+ 4.5V to + 5.5V |
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Symbol |
Parameter |
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Min |
Typ |
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Max |
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Units |
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Conditions |
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VOH |
Output HIGH Voltage |
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2.7 |
3.1 |
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V |
IOH = |
− |
3 mA, VTTL = |
4.75V |
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2.4 |
2.9 |
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IOH = |
− |
3 mA, VTTL = |
4.50V |
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VOL |
Output LOW Voltage |
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0.3 |
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0.5 |
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V |
IOL = |
24 mA, VTTL = |
4.50V |
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VIH |
Input HIGH Voltage |
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− |
1165 |
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− 870 |
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mV |
Guaranteed HIGH Signal for All Inputs |
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VIL |
Input LOW Voltage |
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− |
1830 |
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− 1475 |
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mV |
Guaranteed LOW Signal for All Inputs |
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IIH |
Input HIGH Current |
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350 |
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µ A |
VIN = |
VIH (Max) |
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IIL |
Input LOW Current |
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0.50 |
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µ A |
VIN = |
VIL (Min) |
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IOZHT |
3-STATE Current Output HIGH |
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70 |
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µ A |
VOUT = |
+ |
2.7V |
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IOZLT |
3-STATE Current Output LOW |
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− 700 |
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µ A |
VOUT = |
+ |
0.5V |
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IOS |
Output Short-Circuit Current |
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− 150 |
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− 60 |
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mA |
VOUT = |
0.0V, VTTL = |
+ 5.5V |
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ITTL |
VTTL Supply Current |
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74 |
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mA |
TTL Outputs LOW |
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49 |
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mA |
TTL Outputs HIGH |
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67 |
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mA |
TTL Outputs in 3-STATE |
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DIP TTL-to-ECL AC Electrical Characteristics (Note 9)
VEE = − 4.2V to − 5.7V, VTTL = |
+ 4.5V to + 5.5V, VCC = |
VCCA = |
GND |
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Symbol |
Parameter |
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TC = 0° C |
TC = 25° C |
TC = 85° C |
Units |
Conditions |
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Min |
Max |
Min |
Max |
Min |
Max |
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tPLH |
TN to En |
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1.1 |
3.5 |
1.1 |
3.6 |
1.1 |
3.8 |
ns |
Figures 1, 2 |
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tPHL |
(Transparent) |
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tPLH |
LE to En |
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1.7 |
3.6 |
1.7 |
3.7 |
1.9 |
3.9 |
ns |
Figures 1, 2 |
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tPHL |
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tPZH |
OE to En |
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1.3 |
4.2 |
1.5 |
4.4 |
1.7 |
4.8 |
ns |
Figures 1, 2 |
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(Cutoff to HIGH) |
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tPHZ |
OE to En |
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1.5 |
4.5 |
1.6 |
4.5 |
1.6 |
4.6 |
ns |
Figures 1, 2 |
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(HIGH to Cutoff) |
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tPHZ |
DIR to En |
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1.6 |
4.3 |
1.6 |
4.3 |
1.7 |
4.5 |
ns |
Figures 1, 2 |
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(HIGH to Cutoff) |
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tSET |
Tn to LE |
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1.1 |
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1.1 |
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1.1 |
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ns |
Figures 1, 2 |
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tHOLD |
Tn to LE |
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1.1 |
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1.1 |
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1.1 |
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ns |
Figures 1, 2 |
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tPW(H) |
Pulse Width LE |
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2.1 |
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2.1 |
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2.1 |
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ns |
Figures 1, 2 |
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tTLH |
Transition Time |
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0.6 |
1.6 |
0.6 |
1.6 |
0.6 |
1.6 |
ns |
Figures 1, 2 |
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tTHL |
20% to 80%, 80% to 20% |
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Note 9: The specified limits represent the “worst” case value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions.
www.fairchildsemi.com |
4 |
Commercial Version (Continued)
DIP ECL-to-TTL AC Electrical Characteristics
VEE = − 4.2V to − 5.7V, VTTL = |
+ 4.5V to + 5.5V, VCC = |
VCCA = |
GND, CL = |
50 pF |
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Symbol |
Parameter |
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TC = 0° C |
TC = 25° C |
TC = 85° C |
Units |
Conditions |
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Min |
Max |
Min |
Max |
Min |
Max |
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tPLH |
En to Tn |
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2.3 |
5.6 |
2.4 |
5.6 |
2.6 |
5.9 |
ns |
Figures 3, 4 |
tPHL |
(Transparent) |
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tPLH |
LE to Tn |
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3.1 |
7.2 |
3.1 |
7.2 |
3.3 |
7.7 |
ns |
Figures 3, 4 |
tPHL |
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tPZH |
OE to Tn |
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3.4 |
8.45 |
3.7 |
8.95 |
4.0 |
9.7 |
ns |
Figures 3, 5 |
tPZL |
(Enable Time) |
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3.8 |
9.2 |
4.0 |
9.2 |
4.3 |
9.95 |
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tPHZ |
OE to Tn |
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3.2 |
8.95 |
3.3 |
8.95 |
3.5 |
9.2 |
ns |
Figures 3, 5 |
tPLZ |
(Disable Time) |
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3.0 |
7.7 |
3.4 |
8.7 |
4.1 |
9.95 |
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tPHZ |
DIR to Tn |
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2.7 |
8.2 |
2.8 |
8.7 |
3.1 |
8.95 |
ns |
Figures 3, 6 |
tPLZ |
(Disable Time) |
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2.8 |
7.45 |
3.1 |
7.95 |
4.0 |
9.2 |
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tSET |
En to LE |
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1.1 |
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1.1 |
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1.1 |
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ns |
Figures 3, 6 |
tHOLD |
En to LE |
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2.1 |
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2.1 |
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2.6 |
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ns |
Figures 3, 4 |
tPW(H) |
Pulse Width LE |
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4.1 |
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4.1 |
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4.1 |
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ns |
Figures 3, 7 |
SOIC and PLCC TTL-to-ECL AC Electrical Characteristics
VEE = − 4.2V to − 5.7V, VTTL = + 4.5V to + |
5.5V |
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Symbol |
Parameter |
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TC = 0° C |
TC = 25° C |
TC = 85° C |
Units |
Conditions |
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Min |
Max |
Min |
Max |
Min |
Max |
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tPLH |
Tn to En |
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1.1 |
3.3 |
1.1 |
3.4 |
1.1 |
3.6 |
ns |
Figures 1, 2 |
tPHL |
(Transparent) |
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tPLH |
LE to En |
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1.7 |
3.4 |
1.7 |
3.5 |
1.9 |
3.7 |
ns |
Figures 1, 2 |
tPHL |
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tPZH |
OE to En |
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1.3 |
4.0 |
1.5 |
4.2 |
1.7 |
4.6 |
ns |
Figures 1, 2 |
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(Cutoff to HIGH) |
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tPHZ |
OE to En |
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1.5 |
4.3 |
1.6 |
4.3 |
1.6 |
4.4 |
ns |
Figures 1, 2 |
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(HIGH to Cutoff) |
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tPHZ |
DIR to En |
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1.6 |
4.1 |
1.6 |
4.1 |
1.7 |
4.3 |
ns |
Figures 1, 2 |
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(HIGH to Cutoff) |
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tSET |
Tn to LE |
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1.0 |
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1.0 |
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1.0 |
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ns |
Figures 1, 2 |
tHOLD |
Tn to LE |
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1.0 |
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1.0 |
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1.0 |
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ns |
Figures 1, 2 |
tPW(H) |
Pulse Width LE |
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2.0 |
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2.0 |
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2.0 |
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ns |
Figures 1, 2 |
tTLH |
Transition Time |
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0.6 |
1.6 |
0.6 |
1.6 |
0.6 |
1.6 |
ns |
Figures 1, 2 |
tTHL |
20% to 80%, 80% to 20% |
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tOSHL |
Maximum Skew Common Edge |
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PLCC Only |
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Output-to-Output Variation |
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200 |
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200 |
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200 |
ps |
(Note 10) |
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Data to Output Path |
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tOSLH |
Maximum Skew Common Edge |
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PLCC Only |
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Output-to-Output Variation |
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200 |
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200 |
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200 |
ps |
(Note 10) |
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Data to Output Path |
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tOST |
Maximum Skew Opposite Edge |
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PLCC Only |
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Output-to-Output Variation |
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650 |
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650 |
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650 |
ps |
(Note 10) |
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Data to Output Path |
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tPS |
Maximum Skew |
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PLCC Only |
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Pin (Signal) Transition Variation |
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650 |
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650 |
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650 |
ps |
(Note 10) |
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Data to Output Path |
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Note 10: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite directions both HL and LH (tOST). Parameters tOST and tps guaranteed by design.
100328
5 |
www.fairchildsemi.com |
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