July 1988
Revised August 2000
100350
Low Power Hex D-Type Latch
General Description
The 100350 contains six D-type latches with true and com- plement outputs, a pair of common Enables (Ea and Eb), and a common Master Reset (MR). A Q output follows its D input when both Ea and Eb are LOW. When either Ea or Eb (or both) are HIGH, a latch stores the last valid data present on its D input before Ea or Eb went HIGH. The MR input overrides all other inputs and makes the Q outputs LOW. All inputs have 50 kΩ pull-down resistors.
Features
■20% power reduction of the 100150
■2000V ESD protection
■Pin/function compatible with 100150
■Voltage compensated operating range = − 4.2V to − 5.7V
Ordering Code:
Order Number |
Package Number |
Package Description |
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100350PC |
N24E |
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide |
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100350QC |
V28A |
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square |
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Devises also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol |
Connection Diagrams |
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24-Pin DIP |
Pin Descriptions
28-Pin PLCC
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Pin Names |
Description |
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D0–D5 |
Data Inputs |
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b |
Common Enable Inputs (Active LOW) |
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E |
a, |
E |
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MR |
Asynchronous Master Reset Input |
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Q0–Q5 |
Data Outputs |
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5 |
Complementary Data Outputs |
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Q |
0–Q |
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Latch Type-D Hex Power Low 100350
© 2000 Fairchild Semiconductor Corporation |
DS009884 |
www.fairchildsemi.com |
100350
Truth Tables
(Each Latch)
Latch Operation
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Inputs |
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Outputs |
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Dn |
Ea |
Eb |
MR |
Qn |
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L |
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L |
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L |
L |
L |
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H |
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L |
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L |
L |
H |
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X |
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H |
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X |
L |
Latched (Note 1) |
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X |
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X |
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H |
L |
Latched (Note 1) |
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H = |
HIGH Voltage Level |
L = |
LOW Voltage Level |
X = |
Don’t Care |
Note 1: Retains data present before E positive transition
Asynchronous Operation
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Inputs |
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Outputs |
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Dn |
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Ea |
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Eb |
MR |
Qn |
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X |
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X |
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X |
H |
L |
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Logic Diagram
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 2)
Above which the useful life may be impaired.
Storage Temperature (TSTG) |
− 65° C to + 150° C |
Maximum Junction Temperature (TJ) |
+ 150° C |
VEE Pin Potential to Ground Pin |
− 7.0V to + 0.5V |
Input Voltage (DC) |
VEE to + 0.5V |
Output Current (DC Output HIGH) |
− 50 mA |
ESD (Note 3) |
≥ 2000V |
Recommended Operating
Conditions
Case Temperature (TC) |
0° C to + 85° C |
Supply Voltage (VEE) |
− 5.7V to − 4.2V |
Note 2: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation.
Note 3: ESD testing conforms to MIL-STD-883, Method 3015.
DC Electrical Characteristics |
(Note 4) |
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VEE = − 4.5V to − 5.7V, VCC = VCCA = |
GND, TC = 0° C to + 85° C |
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Symbol |
Parameter |
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Min |
Typ |
Max |
Units |
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Conditions |
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VOH |
Output HIGH Voltage |
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− |
1025 |
− 955 |
− 870 |
mV |
VIN = |
VIH (Max) |
Loading with |
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VOL |
Output LOW Voltage |
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− |
1830 |
− 1705 |
− 1620 |
or VIL (Min) |
50Ω to − |
2.0V |
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VOHC |
Output HIGH Voltage |
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− |
1035 |
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mV |
VIN = |
VIH (Min) |
Loading with |
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VOLC |
Output LOW Voltage |
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− 1610 |
or VIL (Max) |
50Ω to − |
2.0V |
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VIH |
Input HIGH Voltage |
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− |
1165 |
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− 870 |
mV |
Guaranteed HIGH Signal for All Inputs |
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VIL |
Input LOW Voltage |
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− |
1830 |
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− 1475 |
mV |
Guaranteed LOW Signal for All Inputs |
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IIL |
Input LOW Current |
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0.50 |
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µ A |
VIN = |
VIL (Min) |
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IIH |
Input HIGH Current |
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MR |
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240 |
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Dn |
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240 |
µ A |
VIN = |
VIH (Max) |
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E |
a, |
E |
b |
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240 |
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IEE |
Power Supply |
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Inputs Open |
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Current |
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− 89 |
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− 44 |
mA |
VEE = |
− 4.2V to − 4.8V |
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− 93 |
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− 44 |
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VEE = |
− 4.2V to − 5.7V |
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Note 4: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions.
DIP AC Electrical Characteristics
VEE = − 4.2V to − 5.7V, VCC = VCCA = |
GND |
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Symbol |
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Parameter |
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TC = 0° C |
TC = + 25° C |
TC = + 85° C |
Units |
Conditions |
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Min |
Max |
Min |
Max |
Min |
Max |
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tPLH |
Propagation Delay |
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tPHL |
Dn to Output |
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0.50 |
1.40 |
0.50 |
1.40 |
0.50 |
1.50 |
ns |
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(Transparent Mode) |
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Figures 1, 2 |
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tPLH |
Propagation Delay |
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0.75 |
1.85 |
0.75 |
1.85 |
0.75 |
2.05 |
ns |
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tPHL |
Ea, Eb to Output |
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tPLH |
Propagation Delay |
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0.90 |
2.10 |
0.90 |
2.10 |
0.90 |
2.10 |
ns |
Figures 1, 3 |
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tPHL |
MR to Output |
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tTLH |
Transition Time |
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0.35 |
1.30 |
0.35 |
1.30 |
0.35 |
1.30 |
ns |
Figures 1, 2 |
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tTHL |
20% to 80%, 80% to 20% |
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tS |
Setup Time |
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D0–D5 |
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1.00 |
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1.00 |
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1.00 |
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ns |
Figures 3, 4 |
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MR (Release Time) |
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1.60 |
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1.60 |
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1.60 |
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tH |
Hold Time, D0–D5 |
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0.40 |
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0.40 |
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0.40 |
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ns |
Figure 4 |
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tPW(L) |
Pulse Width LOW |
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2.00 |
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2.00 |
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2.00 |
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ns |
Figure 2 |
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Ea, Eb |
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tPW(H) |
Pulse Width HIGH, MR |
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2.00 |
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2.00 |
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2.00 |
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ns |
Figure 3 |
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100350
3 |
www.fairchildsemi.com |
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