February 1992
Revised August 2000
100398
Quad Differential ECL/TTL Translating Transceiver with Latch
General Description
The 100398 is a quad latched transceiver designed to convert TTL logic levels to differential F100K ECL logic levels and vice versa. This device was designed with the capability of driving a differential 25Ω ECL load with cutoff capability, and will sink a 64 mA TTL load. The 100398 is ideal for mixed technology applications utilizing either an ECL or TTL backplane.
The direction of translation is set by the direction control pin (DIR). The DIR pin on the 100398 accepts TTL logic levels. A TTL LOW on DIR sets up the ECL pins as inputs and TTL pins as outputs. A TTL HIGH on DIR sets up the TTL pins as inputs and ECL pins as outputs.
A LOW on the output enable input pin (OE) holds the ECL output in a cut-off state and the TTL outputs at a high impedance level. A HIGH on the latch enable input (LE) latches the data at both inputs even though only one output is enabled at the time. A LOW on LE makes the latch transparent.
The cut-off state is designed to be more negative than a normal ECL LOW level. This allows the output emitter-fol- lowers to turn off when the termination supply is − 2.0V, presenting a high impedance to the data bus. This high impedance reduces termination power and prevents loss of low state noise margin when several loads share the bus.
The 100398 is designed with FAST TTL output buffers, featuring optimal DC drive and capable of quickly charging and discharging highly capacitive loads. All Inputs have 50 kΩ pull-down resistors.
Features
■Differential ECL input/output structure
■64 mA FAST TTL outputs
■25Ω differential ECL outputs with cut-off
■Bi-directional translation
■2000V ESD protection
■Latched outputs
■3-STATE outputs
■Voltage compensated operating range = − 4.2V to − 5.7V
Ordering Code:
Order Number |
Package Number |
Package Description |
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100398PC |
N24E |
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide |
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100398QC |
V28A |
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square |
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100398QI |
V28A |
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square |
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Industrial Temperature Range (− 40° C to + 85° C) |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
FAST is a registered trademark of Fairchild Semiconductor.
Latch with Transceiver Translating ECL/TTL Differential Quad 100398
© 2000 Fairchild Semiconductor Corporation |
DS010970 |
www.fairchildsemi.com |
100398
Logic Symbol
Connection Diagrams
24-Pin DIP
28-Pin PLCC
Pin Descriptions
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Pin Names |
Description |
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E0–E3 |
ECL Data I/O |
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E0–E3 |
Complementary ECL |
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Data I/O |
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T0–T3 |
TTL Data I/O |
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OE |
Output Enable Input Levels |
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LE |
Latch Enable Input Levels |
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DIR |
Direction Control |
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Input (TTL levels) |
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GNDECL |
ECL Ground |
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GNDECLO |
ECL Output Ground |
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GNDS |
ECL Ground-to-Substrate |
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VEE |
ECL Quiescent Power Supply |
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VEED |
ECL Dynamic Power Supply |
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GNDTTL |
TTL Quiescent Ground |
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GNDTTLD |
TTL Dynamic Ground |
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VTTL |
TTL Quiescent Power Supply |
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VTTLD |
TTL Dynamic Power Supply |
Truth Table |
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LE |
DIR |
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OE |
ECL |
TTL |
Notes |
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Port |
Port |
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0 |
0 |
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0 |
LOW |
Z |
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(Cut-Off) |
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0 |
0 |
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1 |
Input |
Output |
(Note 1)(Note 4) |
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0 |
1 |
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0 |
LOW |
Z |
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(Cut-Off) |
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0 |
1 |
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1 |
Output |
Input |
(Note 2)(Note 4) |
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1 |
0 |
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0 |
Input |
Z |
(Note 1)(Note 3) |
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1 |
0 |
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1 |
Latched |
X |
(Note 1)(Note 3) |
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1 |
1 |
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0 |
Low |
Input |
(Note 2)(Note 3) |
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(Cut-Off) |
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1 |
1 |
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1 |
Latched |
X |
(Note 2)(Note 3) |
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H = |
HIGH Voltage Level |
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L = |
LOW Voltage Level |
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X = |
Don’t Care |
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Z = |
High Impedance |
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Note 1: ECL input to TTL output mode.
Note 2: TTL input to ECL output mode.
Note 3: Retains data present before LE set HIGH.
Note 4: Latch is transparent.
www.fairchildsemi.com |
2 |
Functional Diagram |
Detail |
Note: LE, and OE use TTL logic levels
100398
3 |
www.fairchildsemi.com |
100398
Absolute Maximum Ratings(Note 5)
Storage Temperature (TSTG) |
− 65° C to + 150° C |
Maximum Junction Temperature |
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(TJ) |
+ 150° C |
VEE Pin Potential to Ground Pin |
− 7.0V to + 0.5V |
VTTL Pin Potential to Ground Pin |
− 0.5V to + 6.0V |
ECL Input Voltage (DC) |
VEE to + 0.5V |
ECL Output Current |
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(DC Output HIGH) |
− 50 mA |
TTL Input Voltage (Note 6) |
− 0.5V to + 7.0V |
TTL Input Current (Note 6) |
− 30 mA to + 5.0 mA |
Voltage Applied to Output in |
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HIGH State 3-STATE Output |
− 0.5V to + 5.5V |
Current Applied to TTL |
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Output in LOW State (Max) |
twice the Rated IOL (mA) |
ESD (Note 7) |
≥ 2000V |
Recommended Operating
Conditions
Case Temperature (TC) |
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Commercial |
0° C to + 85° C |
Industrial |
− 40° C to + 85° C |
ECL Supply Voltage (VEE) |
− 5.7V to − 4.2V |
TTL Supply Voltage (VTTL) |
+ 4.5V to + 5.5V |
Note 5: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation.
Note 6: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions.
Note 7: ESD testing conforms to MIL-STD-883, Method 3015.
Commercial Version
TTL-to-ECL DC Electrical Characteristics (Note 9)
VEE = − 4.2V to − 5.7V, GND = 0V, TC = |
0° C to + 85° C, VTTL = |
+ 4.5V to + 5.5V |
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Symbol |
Parameter |
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Min |
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Typ |
Max |
Units |
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Conditions |
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VOH |
Output HIGH Voltage |
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− 1025 |
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− 955 |
− 870 |
mV |
VIN = |
VIH(Max) or VIL(Min) |
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VOL |
Output LOW Voltage |
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− 1830 |
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− 1705 |
− 1620 |
mV |
Loading with 50Ω to − 2V |
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Cutoff Voltage |
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− 2000 |
− 1950 |
mV |
OE and LE LOW, DIR HIGH |
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VIN = |
VIH(Max) or VIL(Min), |
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Loading with 50Ω to − 2V |
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VOHC |
Output HIGH Voltage |
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− 1035 |
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mV |
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Corner Point High |
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VIN = |
VIH(Min) or VIL(Max) |
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VOLC |
Output LOW Voltage |
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− 1610 |
mV |
Loading with 50Ω to − 2V |
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Corner Point Low |
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VIH |
Input HIGH Voltage |
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2.0 |
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5.0 |
V |
Over VTTL, VEE, TC Range |
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VIL |
Input LOW Voltage |
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0 |
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0.8 |
V |
Over VTTL, VEE, TC Range |
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IIH |
Input HIGH Current |
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5.0 |
µ A |
VIN = |
+ 2.7V |
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Breakdown Test |
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0.5 |
mA |
VIN = |
+ 5.5V |
IIL |
Input LOW Current |
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− |
700 |
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µ A |
VIN = |
+ 0.5V |
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VFCD |
Input Clamp |
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− |
1.2 |
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V |
IIN = |
− 18 mA |
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Diode Voltage |
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IEE |
VEE Supply Current |
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− |
99 |
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− 50 |
mA |
LE LOW, OE and DIR HIGH |
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Inputs Open |
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IEEZ |
VEE Supply Current |
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− |
159 |
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− 90 |
mA |
LE and OE LOW, DIR HIGH |
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Inputs Open |
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Note 8: Either voltage limit or current limit is sufficient to protect inputs.
Note 9: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions.
www.fairchildsemi.com |
4 |
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