Fairchild Semiconductor 100363QIX, 100363QI, 100363QCX, 100363QC, 100363PC Datasheet

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October 1989

Revised August 2000

100363

Low Power Dual 8-Input Multiplexer

General Description

The 100363 is a dual 8-input multiplexer. The Data Select (Sn) inputs determine which bit (An and Bn) will be presented at the outputs (Za and Zb respectively). The same bit (0–7) will be selected for both the Za and Zb output. All inputs have 50 kΩ pull-down resistors.

Features

50% power reduction of the 100163

2000V ESD protection

Pin/function compatible with 100163

Voltage compensated operating range = − 4.2V to − 5.7V

Available to industrial grade temperature range

Ordering Code:

Order Number

Package Number

Package Description

 

 

 

100363PC

N24E

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide

 

 

 

100363QC

V28A

28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

 

 

 

100363QI

V28A

28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

 

 

Industrial Temperature Range (− 40° C to + 85° C)

 

 

 

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol

Connection Diagrams

 

24-Pin DIP

Pin Descriptions

Pin Names

Description

 

 

 

 

S0–S2

Data Select Inputs

 

A0–A7

A Data Inputs

28-Pin PLCC

B0–B7

B Data Inputs

 

Za, Zb

Data Outputs

 

Multiplexer Input-8 Dual Power Low 100363

© 2000 Fairchild Semiconductor Corporation

DS010612

www.fairchildsemi.com

Fairchild Semiconductor 100363QIX, 100363QI, 100363QCX, 100363QC, 100363PC Datasheet

100363

Truth Table

 

 

 

 

 

Inputs

 

 

 

 

 

Outputs

 

Select

 

 

 

 

Data

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

S2

S1

S0

A7

A6

A5

A4

A3

A2

A1

A0

Za

 

 

 

B7

B6

B5

B4

B3

B2

B1

B0

Zb

L

L

L

 

 

 

 

 

 

 

L

L

L

L

L

 

 

 

 

 

 

 

H

H

 

 

 

 

 

 

 

 

 

 

 

 

L

L

H

 

 

 

 

 

 

L

 

L

L

L

H

 

 

 

 

 

 

H

 

H

 

 

 

 

 

 

 

 

 

 

 

 

L

H

L

 

 

 

 

 

L

 

 

L

L

H

L

 

 

 

 

 

H

 

 

H

 

 

 

 

 

 

 

 

 

 

 

 

L

H

H

 

 

 

 

L

 

 

 

L

L

H

H

 

 

 

 

H

 

 

 

H

 

 

 

 

 

 

 

 

 

 

 

 

H

L

L

 

 

 

L

 

 

 

 

L

H

L

L

 

 

 

H

 

 

 

 

H

 

 

 

 

 

 

 

 

 

 

 

 

H

L

H

 

 

L

 

 

 

 

 

L

H

L

H

 

 

H

 

 

 

 

 

H

 

 

 

 

 

 

 

 

 

 

 

 

H

H

L

 

L

 

 

 

 

 

 

L

H

H

L

 

H

 

 

 

 

 

 

H

 

 

 

 

 

 

 

 

 

 

 

 

H

H

H

L

 

 

 

 

 

 

 

L

H

H

H

H

 

 

 

 

 

 

 

H

H = HIGH Voltage Level

L = LOW Voltage Level

Blank = X = Don’t Care

Logic Diagram

www.fairchildsemi.com

2

Absolute Maximum Ratings(Note 1)

Storage Temperature (TSTG)

− 65° C to + 150° C

Maximum Junction Temperature (TJ)

+ 150° C

VEE Pin Potential to Ground Pin

− 7.0V to + 0.5V

Input Voltage (DC)

VEE to + 0.5V

Output Current (DC Output HIGH)

− 50 mA

ESD (Note 2)

≥ 2000V

Recommended Operating

Conditions

Case Temperature (TC)

 

Commercial

0° C to + 85° C

Industrial

− 40° C to + 85° C

Supply Voltage (VEE)

− 5.7V to − 4.2V

Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Note 2: ESD testing conforms to MIL-STD-883, Method 3015.

Commercial Version

DC Electrical Characteristics (Note 3)

VEE = − 4.2V to − 5.7V, VCC = VCCA =

GND, TC = 0° C to + 85° C

 

 

 

 

 

 

Symbol

Parameter

 

Min

Typ

Max

Units

 

 

Conditions

 

 

 

 

 

 

 

 

 

 

 

VOH

Output HIGH Voltage

 

− 1025

− 955

− 870

mV

VIN =

VIH (Max)

 

Loading with

VOL

Output LOW Voltage

 

− 1830

− 1705

− 1620

mV

or VIL (Min)

 

50Ω to − 2.0V

VOHC

Output HIGH Voltage

 

− 1035

 

 

mV

VIN =

VIH (Min)

 

Loading with

VOLC

Output LOW Voltage

 

 

 

− 1610

mV

or VIL (Max)

 

50Ω to − 2.0V

VIH

Input HIGH Voltage

 

− 1165

 

− 870

mV

Guaranteed HIGH Signal for All Inputs

VIL

Input LOW Voltage

 

− 1830

 

− 1475

mV

Guaranteed LOW Signal for All Inputs

IIL

Input LOW Current

 

0.50

 

 

µ A

VIN =

VIL (Min)

 

 

IIH

Input HIGH Current

 

 

 

 

 

 

 

 

 

 

 

Sn

 

 

265

µ A

VIN =

VIH (Max)

 

 

 

 

An, Bn

 

 

340

 

 

 

 

 

IEE

Power Supply Current

 

− 80

 

− 40

mA

Inputs OPEN

 

 

Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions.

DIP AC Electrical Characteristics

VEE = − 4.2V to − 5.7V, VCC = VCCA = GND

Symbol

Parameter

TC = 0° C

TC = + 25° C

TC = + 85° C

Units

Conditions

 

 

Min

Max

Min

Max

Min

Max

 

 

 

 

 

 

 

 

 

 

 

 

tPLH

Propagation Delay

0.70

1.65

0.80

1.70

0.80

1.80

ns

 

tPHL

A0–A7, B0–B7 to Output

 

 

 

 

 

 

 

 

 

tPLH

Propagation Delay

1.30

2.60

1.40

2.70

1.40

2.70

ns

Figures 1, 2

tPHL

S0–S2 to Output

 

 

 

 

 

 

 

 

tTLH

Transition Time

0.45

1.30

0.45

1.30

0.45

1.30

ns

 

tTHL

20% to 80%, 80% to 20%

 

 

 

 

 

 

 

 

 

PLCC AC Electrical Characteristics

VEE = − 4.2V to − 5.7V, VCC = VCCA = GND

Symbol

Parameter

TC = 0° C

TC = + 25° C

TC = + 85° C

Units

Conditions

 

 

Min

Max

Min

Max

Min

Max

 

 

 

 

 

 

 

 

 

 

 

 

tPLH

Propagation Delay

0.70

1.65

0.80

1.70

0.80

1.80

ns

 

tPHL

A0–A7, B0–B7 to Output

 

 

 

 

 

 

 

 

 

tPLH

Propagation Delay

1.30

2.60

1.40

2.70

1.40

2.70

ns

Figures 1, 2

tPHL

S0–S2 to Output

 

 

 

 

 

 

 

 

tTLH

Transition Time

0.45

1.30

0.45

1.30

0.45

1.30

ns

 

tTHL

20% to 80%, 80% to 20%

 

 

 

 

 

 

 

 

 

100363

3

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