Fairchild Semiconductor 100344QIX, 100344QI, 100344QCX, 100344QC, 100344PC Datasheet

0 (0)

July 1988

Revised August 2000

100344

Low Power 8-Bit Latch with Cut-Off Drivers

General Description

The 100344 contains eight D-type latches, individual inputs (Dn), outputs (Qn), a common enable pin (E), latch enable

(LE), and output enable pin (OEN). A Q output follows its D input when both E and LE are LOW. When either E or LE (or both) are HIGH, a latch stores the last valid data present on its D input prior to E or LE going HIGH.

A HIGH on OEN holds the outputs in a cut-off state. The cut-off state is designed to be more negative than a normal ECL LOW level. This allows the output emitter-followers to turn off when the termination supply is − 2.0V, presenting a high impedance to the data bus. This high impedance reduces termination power and prevents loss of low state noise margin when several loads share the bus.

The 100344 outputs are designed to drive a doubly terminated 50Ω transmission line (25Ω load impedance). All inputs have 50 kΩ pull-down resistors.

Features

Cut-off drivers

Drives 25Ω load

Low power operation

2000V ESD protection

Voltage compensated operating range = − 4.2V to − 5.7V

Ordering Code:

Order Number

Package Number

Package Description

 

 

 

100344PC

N24E

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide

 

 

 

100344QC

V28A

28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

 

 

 

100344QI

V28A

28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

 

 

Industrial Temperature Range (− 40° C to + 85° C)

 

 

 

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagrams

24-Pin DIP 28-Pin PLCC

Logic Symbol

Drivers Off-Cut with Latch Bit-8 Power Low 100344

© 2000 Fairchild Semiconductor Corporation

DS009883

www.fairchildsemi.com

Fairchild Semiconductor 100344QIX, 100344QI, 100344QCX, 100344QC, 100344PC Datasheet

100344

Pin Descriptions

 

Pin Names

Description

 

 

 

 

D0–D7

Data Inputs

 

 

 

 

Enable Input

 

E

 

 

 

 

 

 

Latch Enable Input

 

LE

 

 

 

 

Output Enable Input

 

OEN

 

 

Q0–Q7

Data Outputs

 

 

 

 

 

 

Logic Diagram

Truth Table

 

 

Inputs

 

 

 

 

 

Outputs

 

 

 

 

 

 

 

 

 

 

 

Dn

 

 

E

 

LE

 

OEN

 

Qn

L

 

 

L

 

L

 

L

 

L

H

 

 

L

 

L

 

L

 

H

X

 

H

 

X

 

L

 

Latched (Note 1)

X

 

 

X

 

H

 

L

 

Latched (Note 1)

X

 

 

X

 

X

 

H

 

Cutoff

 

 

 

 

 

 

 

 

 

H = HIGH Voltage level

 

 

 

 

 

 

L = LOW Voltage level

 

 

 

 

 

 

Cutoff =

lower-than-LOW state

 

 

 

X = Don’t Care

Note 1: Retains data present before either LE or E go HIGH.

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2

Absolute Maximum Ratings(Note 2)

Storage Temperature (TSTG)

− 65° C to + 150° C

Maximum Junction Temperature (TJ)

+ 150° C

VEE Pin Potential to Ground Pin

− 7.0V to + 0.5V

Input Voltage (DC)

VEE to + 0.5V

Output Current (DC Output HIGH)

− 100 mA

ESD (Note 3)

≥ 2000V

Recommended Operating

Conditions

Case Temperature (TC)

 

Commercial

0° C to + 85° C

Industrial

− 40° C to + 85°

Supply Voltage (VEE)

− 5.7V to − 4.2V

Note 2: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Note 3: ESD testing conforms to MIL-STD-883, Method 3015.

Commercial Version

 

 

 

 

 

 

 

 

 

 

 

DC Electrical Characteristics

(Note 4)

 

 

 

 

 

 

 

VEE = − 4.2V to − 5.7V, VCC = VCCA =

GND, TC = 0° C to + 85° C

 

 

 

 

 

 

 

Symbol

Parameter

 

Min

 

Typ

Max

Units

 

Conditions

 

 

 

 

 

 

 

 

 

 

 

 

VOH

Output HIGH Voltage

 

− 1025

 

− 955

− 870

mV

VIN =

VIH (Max)

 

Loading with

VOL

Output LOW Voltage

 

− 1830

 

− 1705

− 1620

mV

or VIL (Min)

25Ω to − 2.0V

VOHC

Output HIGH Voltage

 

− 1035

 

 

 

mV

VIN =

VIH (Min)

 

Loading with

VOLC

Output LOW Voltage

 

 

 

 

− 1610

mV

or VIL (Max)

25Ω to − 2.0V

 

 

 

 

 

 

− 1950

 

VIN =

 

 

 

= HIGH

VOLZ

Cutoff LOW Voltage

 

 

 

 

mV

VIH (Min)

 

OEN

 

 

 

 

 

 

 

 

or VIL (Max)

 

 

 

VIH

Input HIGH Voltage

 

− 1165

 

 

− 870

mV

Guaranteed HIGH Signal for All Inputs

VIL

Input LOW Voltage

 

− 1830

 

 

− 1475

mV

Guaranteed LOW Signal for All Inputs

IIL

Input LOW Current

 

0.50

 

 

 

µ A

VIN =

VIL (Min)

 

 

 

IIH

Input HIGH Current

 

 

 

 

240

µ A

VIN =

VIH (Max)

 

 

 

IEE

Power Supply Current

 

 

 

 

 

 

Inputs Open

 

 

 

 

 

 

− 178

 

 

− 85

mA

VEE =

− 4.2V to − 4.8V

 

 

 

 

 

 

− 185

 

 

− 85

 

VEE =

− 4.2V to − 5.7V

 

 

 

Note 4: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions.

AC Electrical Characteristics

VEE = − 4.2V to − 5.7V, VCC =

VCCA = GND

 

 

 

 

 

 

 

 

Symbol

 

 

 

Parameter

TC = 0° C

TC = + 25° C

TC = + 85° C

Units

Conditions

 

 

 

 

 

 

Min

Max

Min

Max

Min

Max

 

 

 

 

 

 

 

 

 

 

 

 

 

tPLH

Propagation Delay

 

0.90

2.10

0.90

2.10

1.00

2.30

ns

Figures 1, 2

tPHL

Dn to Output

 

(Note 5)

 

 

 

 

 

 

 

 

tPLH

Propagation Delay

 

1.60

3.10

1.60

3.10

1.80

3.40

ns

Figures 1, 4

 

 

 

 

 

 

 

tPHL

LE, E to Output

 

(Note 5)

 

 

 

 

 

 

 

 

tPZH

Propagation Delay

 

1.60

4.20

1.60

4.20

1.60

4.20

ns

Figures 1, 2

 

 

 

 

 

 

 

 

 

 

 

 

 

tPHZ

OEN to Output

 

1.00

2.70

1.00

2.70

1.00

2.70

(Note 5)

 

 

tTLH

Transition Time

 

0.45

2.00

0.45

2.00

0.45

2.00

ns

Figures 1, 3

tTHL

20% to 80%, 80% to 20%

 

 

 

 

 

 

 

 

tS

Setup Time

D0–D7

1.00

 

1.00

 

1.10

 

ns

Figures 1, 3

tH

Hold Time

D0–D7

0.10

 

0.10

 

0.10

 

ns

Figures 1, 3

tPW(H)

Pulse Width HIGH

 

2.00

 

2.00

 

2.00

 

ns

Figures 1, 3

 

 

 

 

 

 

 

 

 

 

LE, E

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note 5: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching.

100344

3

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