Fairchild Semiconductor 74AC175SJX, 74AC175SJ, 74AC175SCX, 74AC175SC, 74AC175PC Datasheet

© 1999 Fairchild Semiconductor Corporation DS009936 www.fairchildsemi.com

November 1988

Revised November 1999

74AC175 • 74ACT175 Quad D-Type Flip-Flop

74AC175 • 74ACT175

Quad D-Type Flip-Flop

General Description

The AC/ACT175 is a hi g h-s pee d q uad D - type fli p- flop. The

device is useful for general flip-flop requirements where

clock and clear inputs are common. The information on the

D-type inputs is stored during the LOW-to-HIGH clock tran-

sition. Both true and comple mented outputs of each flip-

flop are provided. A Master Reset input resets all flip-flops,

independent of the Clock or D-type inputs, when LOW.

Features

■ I

CC

reduced by 50%

■ Edge-triggered D-type inputs

■ Buffered positive edge-triggered cl ock

■ Asynchronous common reset

■ True and complement output

■ Outputs source/sink 24 mA

■ ACT175 has TTL-compatible inputs

Ordering Code:

Device also available in Tape and Reel. Specify by appending s uffix let te r “X” to the ordering code.

Logic Symbols

IEEE/IEC

Connection Diagram

Pin Descriptions

FACT is a trademark of Fairchild Semiconductor Corporation.

Order Number Package Number Package Description

74AC175SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body

74AC175SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74AC175MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74AC175PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

74ACT175SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body

74ACT175SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74ACT175MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74ACT175PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Pin Names Description

D

0

–D

3

Data Inputs

CP Clock Pulse Input

MR

Master Reset Input

Q

0

–Q

3

True Outputs

Q

0

–Q

3

Complement Outputs

www.fairchildsemi.com 2

74AC175 • 74ACT175

Functional Description

The AC/ACT175 consists of four edge-triggered D-type flip-

flops with individual D i nputs and Q and Q

outputs. The

Clock and Master Re set are common. The four f lip-flops

will store the state of their individual D inputs on th e LOW-

to-HIGH clock (CP) transi tion, causing ind ividual Q and Q

outputs to follow. A LOW input on the Master Reset (MR)

will force all Q outputs LOW and Q

outputs HIGH indepen-

dent of Clock or Data inputs. The AC/ACT175 is useful for

general logic applic ations where a common Master R eset

and Clock are acceptable.

Tr uth Table

H = HIGH Voltage Level

L = LOW Voltage Level

t

n

= Bit Time before Clock Pulse

t

n+1

= Bit Time after Clock Pulse

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Inputs Outputs

@ t

n

, MR = H@ t

n+1

D

n

Q

n

Q

n

LLH

HHL

3 www.fairchildsemi.com

74AC175 • 74ACT175

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute max imum ratings are those values beyond w hich damage

to the device may occu r. The databook spe cificatio ns shou ld be met, wit h-

out exception, to ensure that the system de sign is relia ble over its p ower

supply, temperature, and output/input loading variables. Fairchild does not

recommend operation of FACT circuits outside databook specif ic at ions

DC Electrical Characteristics for AC

Note 2: All outputs loaded; thres holds on input associate d w it h output under test.

Note 3: Maximum test duration 2.0 ms, one output loaded at a time.

Note 4: I

IN

and I

CC

@ 3.0V are guaranteed to be less than or equa l t o th e respective limit @ 5.5V V

CC

.

Supply Voltage (V

CC

) −0.5V to +7.0V

DC Input Diode Current (I

IK

)

V

I

= −0.5V −20 mA

V

I

= V

CC

+ 0.5V +20 mA

DC Input Voltage (V

I

) −0.5V to V

CC

+ 0.5V

DC Output Diode Current (I

OK

)

V

O

= −0.5V −20 mA

V

O

= V

CC

+ 0.5V +20 mA

DC Output Voltage (V

O

) −0.5V to V

CC

+ 0.5V

DC Output S ource

or Sink Current (I

O

) ± 50 mA

DC V

CC

or Ground Current

per Output Pin (I

CC

or I

GND

) ± 50 mA

Storage Temperature (T

STG

) −65°C to +150°C

Junction Temperature (T

J

)

PDIP 140°C

Supply Voltage (V

CC

)

AC 2.0V to 6.0V

ACT 4.5V to 5.5V

Input Voltage (V

I

)0V to V

CC

Output Voltage (V

O

)0V to V

CC

Operating Temperature (T

A

) −40°C to +85°C

Minimum Input Edge Rate (∆V/∆t)

AC Devices

V

IN

from 30% to 70% of V

CC

V

CC

@ 3.3V, 4.5V, 5.5V 125 mV/ns

Minimum Input Edge Rate (∆V/∆t)

ACT Devices

V

IN

from 0.8V to 2.0V

V

CC

@ 4.5V, 5.5V 125 mV/ns

Symbol Parameter

V

CC

T

A

= +25°CT

A

= −40°C to +85°C

Units Conditions

(V) Typ Guaranteed Limits

V

IH

Minimum HIGH Level 3.0 1.5 2.1 2.1 V

OUT

= 0.1V

Input Voltage 4.5 2.25 3.15 3.15 V or V

CC

− 0.1V

5.5 2.75 3.85 3.85

V

IL

Maximum LOW Level 3.0 1.5 0.9 0.9 V

OUT

= 0.1V

Input Voltage 4.5 2.25 1.35 1.35 V or V

CC

− 0.1V

5.5 2.75 1.65 1.65

V

OH

Minimum HIGH Level 3.0 2.99 2.9 2.9

Output Voltage 4.5 4.49 4.4 4.4 V I

OUT

= −50 µA

5.5 5.49 5.4 5.4

V

IN

= V

IL

or V

IH

3.0 2.56 2.46 I

OH

= −12 mA

4.5 3.86 3.76 V I

OH

= −24 mA

5.5 4.86 4.76 I

OH

= −24 mA (Note 2)

V

OL

Maximum LOW Level 3.0 0.002 0.1 0.1

Output Voltage 4.5 0.001 0.1 0.1 V I

OUT

= 50 µA

5.5 0.001 0.1 0.1

V

IN

= V

IL

or V

IH

3.0 0.36 0.44 I

OL

= 12 mA

4.5 0.36 0.44 V I

OL

= 24 mA

5.5 0.36 0.44 I

OL

= 24 mA (Note 2)

I

IN

(Note 4)

Maximum Input

Leakage Current

5.5 ±0.1 ± 1.0 µAV

I

= V

CC

, GND

I

OLD

Minimum Dynamic 5.5 75 mA V

OLD

= 1.65V Max

I

OHD

Output Current (Note 3) 5.5 −75 mA V

OHD

= 3.85V Min

I

CC

(Note 4)

Maximum Quiescent

Supply Current

5.5 4.0 40.0 µAV

IN

= V

CC

or GND