Fairchild Semiconductor 74ABT574CSCX, 74ABT574CSC, 74ABT574CPC, 74ABT574CMTCX, 74ABT574CMTC Datasheet

November 1992

Revised November 1999

74ABT574

Octal D-Type Flip-Flop with 3-STATE Outputs

General Description

The ABT574 is an octal flip-flop with a buffered common Clock (CP) and a buffered common Output Enable (OE). The information presented to the D inputs is stored in the flip-flops on the LOW-to-HIGH Clock (CP) transition.

The device is functionally identical to the ABT374 but has broadside pinouts.

Features

■Inputs and outputs on opposite sides of package allowing easy interface with microprocessors

■Useful as input or output port for microprocessors

■Functionally identical to ABT374

■3-STATE outputs for bus-oriented applications

■Output sink capability of 64 mA, source capability of 32 mA

■Guaranteed output skew

■Guaranteed multiple output switching specifications

■Output switching specified for both 50 pF and 250 pF loads

■Guaranteed simultaneous switching, noise level and dynamic threshold performance

■Guaranteed latchup protection

■High impedance glitch free bus loading during entire power up and power down cycle

■Non-destructive hot insertion capability

Ordering Code:

Order Number	Package Number	Package Description
74ABT574CSC	M20B	20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ABT574CSJ	M20D	20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT574CMSA	MSA20	20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT574CMTC	MTC20	20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram	Pin Descriptions
	Pin Names			Description
		D0–D7		Data Inputs
		CP		Clock Pulse Input (Active Rising Edge)
				3-STATE Output Enable Input (Active LOW)
		OE
		O0–O7		3-STATE Outputs

Outputs STATE-3 with Flop-Flip Type-D Octal 74ABT574

© 1999 Fairchild Semiconductor Corporation

DS011511

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74ABT574

Functional Description

The ABT574 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH Clock (CP) transition.

With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs are in a high impedance state. Operation of the OE input does not affect the state of the flipflops.

Function Table

		Inputs		Internal	Outputs	Function
		CP	D	Q	O
	OE
	H	H or L	L	NC	Z	Hold
	H	H or L	H	NC	Z	Hold
	H		L	L	Z	Load
	H		H	H	Z	Load
	L		L	L	L	Data Available
	L		H	H	H	Data Available
	L	H or L	L	NC	NC	No Change in Data
	L	H or L	H	NC	NC	No Change in Data

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Z = High Impedance

= LOW-to-HIGH Transition

NC = No Change

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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Absolute Maximum Ratings(Note 1)

Storage Temperature	− 65° C to + 150° C
Ambient Temperature under Bias	− 55° C to + 125° C
Junction Temperature under Bias	− 55° C to + 150° C
VCC Pin Potential to Ground Pin	− 0.5V to + 7.0V
Input Voltage (Note 2)	− 0.5V to + 7.0V
Input Current (Note 2)	− 30 mA to + 5.0 mA
Voltage Applied to Any Output
in the Disabled or
Power-Off State	− 0.5V to 5.5V
in the HIGH State	− 0.5V to VCC
Current Applied to Output
in LOW State (Max)	twice the rated IOL (mA)
DC Latchup Source Current	− 500 mA
Over Voltage Latchup (I/O)	10V

Recommended Operating

Conditions

Free Air Ambient Temperature	− 40° C to + 85° C
Supply Voltage	+ 4.5V to + 5.5V
Minimum Input Edge Rate (∆ V/∆ t)
Data Input	50 mV/ns
Enable Input	20 mV/ns
Clock Input	100 mV/ns

Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.

Note 2: Either voltage limit or current limit is sufficient to protect inputs.

DC Electrical Characteristics

Symbol

Parameter

Min

Typ

Max

Units

VCC

Conditions

VIH

Input HIGH Voltage

2.0

V

Recognized HIGH Signal

VIL

Input LOW Voltage

0.8

V

Recognized LOW Signal

VCD

Input Clamp Diode Voltage

− 1.2

V

Min

IIN =

− 18 mA

VOH

Output HIGH Voltage

2.5

V

Min

IOH =

−

3 mA

2.0

V

Min

IOH =

−

32 mA

VOL

Output LOW Voltage

0.55

IOL =

64 mA

IIH

Input HIGH Current

1

µ A

Max

VIN =

2.7V (Note 3)

1

VIN =

VCC

IBVI

Input HIGH Current Breakdown Test

7

µ A

Max

VIN =

7.0V

IIL

Input LOW Current

− 1

µ A

Max

VIN =

0.5V (Note 3)

− 1

VIN =

0.0V

VID

Input Leakage Test

4.75

V

0.0

IID =

1.9 µ A

All Other Pins Grounded

IOZH

Output Leakage Current

10

µ A

0 −

5.5V

VOUT =

2.7V;

=

OE

2.0V

IOZL

Output Leakage Current

− 10

µ A

0 −

5.5V

VOUT =

0.5V;

=

OE

2.0V

IOS

Output Short-Circuit Current

− 100

− 275

mA

Max

VOUT =

0.0V

ICEX

Output High Leakage Current

50

µ A

Max

VOUT =

VCC

IZZ

Bus Drainage Test

100

µ A

0.0

VOUT =

5.5V; All Other GND

ICCH

Power Supply Current

50

µ A

Max

All Outputs HIGH

ICCL

Power Supply Current

30

mA

Max

All Outputs LOW

ICCZ

Power Supply Current

50

µ A

Max

=

VCC

OE

All Others at VCC or GND

ICCT

Additional ICC/Input

Outputs Enabled

2.5

mA

VI = VCC − 2.1V

Outputs 3-STATE

2.5

mA

Max

Enable Input VI = VCC − 2.1V

Outputs 3-STATE

2.5

mA

Data Input VI = VCC − 2.1V

All Others at VCC or GND

ICCD

Dynamic ICC

No Load

mA/

Outputs Open,

= GND,

Max

OE

(Note 3)

0.30

MHz

One Bit Toggling (Note 4),

50% Duty Cycle

Note 3: Guaranteed, but not tested.

Note 4: For 8-bit toggling, ICCD < 0.8 mA/MHz.

74ABT574

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