Fairchild Semiconductor 74ABT273CSJX, 74ABT273CSJ, 74ABT273CSC, 74ABT273CMTCX, 74ABT273CMTC Datasheet

January 1993

Revised November 1999

74ABT273

Octal D-Type Flip-Flop

General Description

The ABT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.

The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output.

All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.

Features

■Eight edge-triggered D-type flip-flops

■Buffered common clock

■Buffered, asynchronous Master Reset

■See ABT377 for clock enable version

■See ABT373 for transparent latch version

■See ABT374 for 3-STATE version

■Output sink capability of 64 mA, source capability of 32 mA

■Guaranteed latchup protection

■High impedance glitch free bus loading during entire power up and power down cycle

■Non-destructive hot insertion capability

■Disable time less than enable time to avoid bus contention

Ordering Code:

Order Number	Package Number	Package Description
74ABT273CSC	M20B	20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ABT273CSJ	M20D	20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT273CMSA	MSA20	20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT273CMTC	MTC20	20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram	Pin Descriptions
			Pin Names		Description
			D0–D7		Data Inputs
					Master Reset (Active LOW)
			MR
			CP		Clock Pulse Input (Active Rising Edge)
			Q0–Q7		Data Outputs

Flop-Flip Type-D Octal 74ABT273

© 1999 Fairchild Semiconductor Corporation

DS011549

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74ABT273

Truth Table

		Operating Mode					Inputs		Output
				MR			CP	Dn	Qn
		Reset (Clear)		L			X	X	L
		Load “1”		H				h	H
		Load “0”		H				l	L
H =
	HIGH Voltage Level steady state
h =	HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition
L =	LOW Voltage Level steady state
I =	LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition
X =	Immaterial

= LOW-to-HIGH clock transition

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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Absolute Maximum Ratings(Note 1)

Storage Temperature	− 65° C to + 150° C
Ambient Temperature under Bias	− 55° C to + 125° C
Junction Temperature under Bias	− 55° C to + 150° C
VCC Pin Potential to Ground Pin	− 0.5V to + 7.0V
Input Voltage (Note 2)	− 0.5V to + 7.0V
Input Current (Note 2)	− 30 mA to + 5.0 mA
Voltage Applied to Any Output
in the Disabled or
Power-Off State	− 0.5V to + 4.75V
in the HIGH State	− 0.5V to VCC
Current Applied to Output
in LOW State (Max)	twice the rated IOL (mA)
DC Latchup Source Current	− 500 mA
(Across Comm Operating Range)
Over Voltage Latchup	VCC + 4.5V

Recommended Operating

Conditions

Free Air Ambient Temperature	− 40° C to + 85° C
Supply Voltage	+ 4.5V to + 5.5V
Minimum Input Edge Rate (∆ V/∆ t)
Data Input	50 mV/ns
Enable Input	20 mV/ns

Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.

Note 2: Either voltage limit or current limit is sufficient to protect inputs.

DC Electrical Characteristics

Symbol	Parameter		Min	Typ	Max	Units	VCC			Conditions
VIH	Input HIGH Voltage		2.0			V		Recognized HIGH Signal
VIL	Input LOW Voltage				0.8	V		Recognized LOW Signal
VCD	Input Clamp Diode Voltage				− 1.2	V	Min	IIN =	− 18 mA
VOH	Output HIGH Voltage		2.5			V	Min	IOH =	−	3 mA
			2.0					IOH =	−	32 mA
VOL	Output LOW Voltage				0.55	V	Min	IOL =	64 mA
IIH	Input HIGH Current				1	µ A	Max	VIN =	2.7V (Note 3)
					1			VIN =	VCC
IBVI	Input HIGH Current				7	µ A	Max	VIN =	7.0V
	Breakdown Test
IIL	Input LOW Current				− 1	µ A	Max	VIN =	0.5V (Note 3)
					− 1			VIN =	0.0V
VID	Input Leakage Test		4.75			V	0.0	IID =	1.9 µ A
								All Other Pins Grounded
IOS	Output Short-Circuit Current		− 100		− 275	mA	Max	VOUT =		0.0V
ICEX	Output HIGH Leakage Current				50	µ A	Max	VOUT =		VCC
ICCH	Power Supply Current				50	µ A	Max	All Outputs HIGH
ICCL	Power Supply Current				30	mA	Max	All Outputs LOW
ICCT	Maximum ICC/Input	Outputs Enabled			1.5	mA	Max	VI =	VCC − 2.1V
								Data Input VI = VCC − 2.1V
								All Others at VCC or GND
ICCD	Dynamic ICC	No Load			0.3	mA/	Max	Outputs Open (Note 4)
						MHz		One Bit Toggling, 50% Duty Cycle

Note 3: Guaranteed but not tested.

Note 4: For 8 bits toggling, ICCD < 0.5 mA/MHz.

74ABT273

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